Deep Trench Isolation Structure for CMOS Image Sensors
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Solution Overview
Problem
Conventional CMOS image sensor pixels are susceptible to blooming and increased dark current due to scallop-shaped recesses in deep trench isolation structures, which lead to current leakage and cross-talk between neighboring pixels, especially in infrared imaging applications where light penetration is deeper.
Innovation Solution
The implementation of a deep trench isolation structure with a lower deep trench region and an upper shallow trench region, where the shallow trench has tapered or vertical sidewalls to remove scallop-shaped recesses, reducing current leakage and dark current by providing electrical isolation between pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench isolation structures are used in CMOS image sensors, then electrical isolation between pixels is improved, but scallop-shaped recesses in trench sidewalls cause current leakage and increased dark current
Solution Approach 1:
The patent changes the geometric parameters of the trench sidewalls by introducing tapered portions with specific angles (e.g., 15-45 degrees) and controlled depths (e.g., 0.1-2.0 micrometers). This parameter modification eliminates the scallop-shaped recesses that cause current leakage while maintaining the electrical isolation function, thereby reducing dark current without sacrificing pixel isolation reliability
Solution Approach 2:
The patent introduces asymmetric features into the trench structure by creating tapered portions on the sidewalls that break the symmetric scallop-shaped recesses. This asymmetry in the trench profile prevents the formation of regions susceptible to current leakage, while the overall isolation function is preserved through the maintained trench depth and fill material configuration
2Ease of manufacture
If conventional deep trench structures with scallop-shaped recesses are used, then manufacturing process is simpler, but blooming and cross-talk between neighboring pixels occur
Solution Approach 1:
The patent modifies the trench sidewall parameters by introducing controlled tapers with specific angle ranges (15-45 degrees) and depth specifications (0.1-2.0 micrometers). This parameter change prevents blooming and cross-talk by eliminating the scallop-shaped recesses that facilitate current leakage, while the trench formation process remains compatible with standard CMOS manufacturing techniques
Solution Approach 2:
The patent applies local quality modification by introducing tapered portions only at specific regions of the trench sidewalls where scallop-shaped recesses form. This localized structural modification targets the specific problem areas without requiring complete redesign of the entire trench structure, maintaining manufacturing simplicity while preventing blooming and cross-talk
Data Source
AI summary
Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.