Deep Trench Isolation Etch Sequence to Eliminate Divot Formation
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Solution Overview
Problem
The bipolar-CMOS (BCD) process for manufacturing power devices faces challenges in optimizing electrical performance due to divot formation in semiconductor devices, which results in high leakage current and requires additional etching steps to correct, increasing manufacturing costs.
Innovation Solution
A method is introduced that involves forming a semiconductor device with a deep trench isolation (DTI) structure by etching back the conduction layer after the isolation layer, ensuring the top surface of the conduction layer is at the same level as the isolation layer, thereby preventing divot formation and reducing the need for further etching, which includes sequential steps of forming pad and nitride layers, creating STI and DTI structures, and using specific etching techniques to achieve an inclined boundary between the layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form DTI structure, then isolation layer can be formed, but divot formation occurs causing high leakage current
Solution Approach 1:
The conduction layer is formed with an upper inclined boundary before the isolation layer is deposited, creating a pre-configured structure that prevents divot formation during subsequent etching processes. This preliminary geometric configuration ensures that when the isolation layer is etched back, the conduction layer's inclined surface guides the etching process to maintain proper alignment and prevent depression formation at the interface.
Solution Approach 2:
The etching process parameters are optimized by controlling the etching depth and angle to match the inclined boundary of the conduction layer. By adjusting the etching parameters (depth, angle, and selectivity), the process is tuned to etch the isolation layer back to the correct level without creating divots, thereby improving reliability while maintaining manufacturing precision.
2Reliability
If additional etching steps are performed to correct divot formation, then leakage current is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The conduction layer is formed with an upper inclined boundary before the isolation layer is deposited, creating a pre-configured structure that prevents divot formation during subsequent etching processes. This preliminary geometric configuration ensures that when the isolation layer is etched back, the conduction layer's inclined surface guides the etching process to maintain proper alignment and prevent depression formation at the interface.
Solution Approach 2:
The invention extracts and eliminates the need for corrective etching steps by incorporating the preventive geometry directly into the conduction layer formation process. By removing the requirement for additional divot-correction steps, the manufacturing process is simplified while maintaining reliable device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates divot formation, enhances semiconductor device performance, and reduces manufacturing costs by avoiding unnecessary etching steps, leading to improved electrical performance and cost efficiency.
Implementation Method 1
etching back the conduction layer after etching back the isolation layer
Data Source
AI summary
A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.