Deep Trench Isolation Doping for Parasitic Transistor Control
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Solution Overview
Problem
Deep trench isolation structures in semiconductor devices often form parasitic transistors due to the use of insulating liners and polysilicon fills, leading to excessive stress and reduced isolation effectiveness, especially in flash memory cells where independent voltage application is crucial.
Innovation Solution
The formation of deep trench isolation structures involves a thin insulating liner lined with a semiconductive material, where a channel stop region is implanted into the bottom surface, and/or the bottom portion is partially filled with an insulating material, or the polysilicon fill is doped with high concentrations of dopants to increase the threshold voltage of the parasitic transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If deep trench isolation structures are filled with insulating liner and polysilicon, then stress is reduced, but parasitic transistors are formed
Solution Approach 1:
The patent applies different doping concentrations at different locations within the polysilicon fill. The bottom portion has higher doping concentration to increase threshold voltage and suppress parasitic transistors, while the top portion has lower doping concentration to minimize stress. This local differentiation resolves the contradiction between stress reduction and parasitic transistor formation.
Solution Approach 2:
The patent changes the doping concentration parameter within the polysilicon fill material. By varying the doping concentration from bottom to top, the patent simultaneously achieves high threshold voltage at the bottom (suppressing parasitic transistors) and low stress overall (maintaining device reliability).
2Reliability
If deep trench isolation structures are filled completely with insulating material, then isolation is improved, but excessive stress is generated
Solution Approach 1:
The patent uses a thin insulating liner only at the bottom portion of the deep trench, rather than completely filling the trench with insulating material. This localized application provides sufficient isolation at the critical bottom region while avoiding the excessive stress that would result from complete filling.
3Stress or pressure
If polysilicon fill is used in deep trench isolation, then stress is minimized, but threshold voltage of parasitic transistor is reduced
Solution Approach 1:
The patent applies high doping concentration specifically to the bottom portion of the polysilicon fill where parasitic transistors form, while keeping the top portion lightly doped. This local differentiation maintains low overall stress while achieving high threshold voltage at the critical bottom region.
Solution Approach 2:
The patent varies the doping concentration parameter within the polysilicon fill, creating a gradient from high concentration at the bottom to low concentration at the top. This parameter change enables simultaneous achievement of high threshold voltage and low stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the threshold voltage of parasitic transistors, enhancing the isolation capabilities of deep trench isolation structures and allowing for independent voltage application to individual flash memory cell P wells without disturbing others.
Implementation Method 1
The P well 42 is formed by implanting the substrate 40 with a first dopant, and the N well 41 is formed by implanting the substrate with a second dopant
Implementation Method 2
semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material
Data Source
AI summary
Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.