Deep Trench Isolation Structure for High Iso BV in BCD Chips

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Solution Overview

Problem

Existing deep trench isolation (DTI) structures in Bipolar-CMOS-DMOS (BCD) technology face limitations in achieving high isolation breakdown voltage (Iso BV) and are vulnerable to process variations.

Innovation Solution

A novel DTI structure with a predetermined depth and inclination, where the width increases from the buried layer to the bottom face, is introduced. This structure includes a gap-fill insulating film and an air gap, optimizing DTI depth, width, and angle to enhance Iso BV and reduce variability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a typical deep trench isolation structure is used, then the chip area is reduced compared to junction isolation, but the isolation breakdown voltage cannot be increased and is vulnerable to process variations

Engineering Contradiction:
Improvechip areaVSAvoidisolation breakdown voltage
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The deep trench isolation structure employs an asymmetric width profile where the trench width varies with depth. Specifically, the trench has a narrower width at the upper portion and a wider width at the lower portion, creating an asymmetric geometry that optimizes both area utilization and electrical isolation performance. This asymmetric design allows the trench to provide sufficient isolation breakdown voltage while maintaining compact chip area.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The invention applies local quality by providing different trench widths at different depths. The upper portion of the trench has a narrower width to save chip area, while the lower portion has a wider width to enhance isolation breakdown voltage. This localized variation in geometric properties allows each region of the trench to serve its specific function optimally.

Inventive Principle:
Principle #3Local quality

2Reliability

If the deep trench isolation depth is increased to improve isolation breakdown voltage, then the manufacturing complexity and process variation sensitivity increase

Engineering Contradiction:
Improveisolation breakdown voltageVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention optimizes the isolation breakdown voltage by carefully controlling geometric parameters of the trench, specifically the width at different depths and the overall trench depth. By adjusting these parameters within optimized ranges, high isolation performance is achieved without requiring excessive trench depth that would complicate manufacturing. The asymmetric width profile is defined by specific dimensional parameters that balance performance and manufacturability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the deep trench isolation width is increased uniformly to improve isolation breakdown voltage, then the chip area occupied by isolation structures increases

Engineering Contradiction:
Improveisolation breakdown voltageVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Rather than using a uniform wide trench that would consume excessive chip area, the invention employs an asymmetric width profile where the trench is narrower at the upper portion and wider at the lower portion. This asymmetric configuration provides sufficient isolation breakdown voltage through the wider lower section while minimizing the area occupied by the narrower upper section, thus optimizing the balance between isolation performance and chip area utilization.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The trench width is locally optimized at different depths: the upper portion has a narrower width to conserve chip area, while the lower portion has a wider width to provide the necessary isolation breakdown voltage. This local differentiation of geometric properties ensures that area is only where needed for electrical isolation, rather than uniformly across the entire trench height.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12349452B2Bipolar-CMOS-DMOS semiconductor device having a deep trench isolation structure for high isolation breakdown voltage
Publication Date: 2025.07.01 SK KEYFOUNDRY INC
  • US12349452B2 patent drawing
  • US12349452B2 patent drawing
  • US12349452B2 patent drawing

AI summary

A semiconductor device including: a semiconductor substrate including a buried layer; and a deep trench isolation a predetermined depth disposed starting from an upper surface of the semiconductor substrate, wherein the deep trench isolation includes: a first point disposed near the upper surface of the semiconductor substrate; a second point disposed near the buried layer; and a third point disposed near a bottom face of the deep trench isolation, and wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point, is disclosed.