Deep Trench Isolation for LDMOS Transistor Arrays
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Solution Overview
Problem
Conventional LDMOS transistor arrays require a large amount of silicon real estate for electrical isolation, leading to inefficient use of space due to the need for significant lateral separation between transistors, which is exacerbated by dopant diffusion during thermal processing.
Innovation Solution
The implementation of deep trench isolation structures, both outer and inner, which are deeper than conventional shallow trench isolation structures and have round corners to minimize stress, along with n-type junction isolation regions that surround portions of the epitaxial layer, significantly reducing the lateral diffusion of dopants and thus the required silicon real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional shallow trench isolation structures are used, then electrical isolation between transistors is achieved, but the lateral spacing between transistors must be large, resulting in inefficient use of silicon space
Solution Approach 1:
The patent transitions from two-dimensional lateral isolation to three-dimensional deep trench isolation by extending isolation structures vertically into the substrate. Deep trench isolation structures reach depths of 5-15 micrometers, creating isolation barriers in the vertical dimension that eliminate the need for large lateral spacing between transistors, thereby improving silicon space utilization while maintaining electrical isolation.
Solution Approach 2:
The patent implements a nested isolation architecture where inner deep trench isolation structures are positioned within outer deep trench isolation structures. This nested configuration creates multiple concentric isolation barriers that enhance electrical isolation effectiveness while optimizing the use of lateral space, allowing transistors to be placed closer together.
2Reliability
If large lateral separation is provided between transistors, then electrical isolation is improved, but the amount of silicon real estate required increases significantly
Solution Approach 1:
The patent moves the isolation function from the lateral plane to the vertical dimension by creating deep trenches that extend 5-15 micrometers into the substrate. This vertical isolation approach provides effective electrical separation between adjacent transistors without requiring large lateral distances, thus reducing silicon real estate consumption while maintaining isolation reliability.
Solution Approach 2:
The patent employs composite isolation structures combining multiple materials including silicon dioxide fill material, silicon nitride liners, and doped semiconductor regions. This composite approach creates highly effective isolation barriers within compact dimensions, achieving superior electrical isolation in a space-efficient manner.
3Ease of manufacture
If dopant diffusion is allowed during thermal processing, then device formation is simplified, but lateral spread of dopants increases, requiring larger separation distances
Solution Approach 1:
The patent applies preliminary anti-action by forming deep trench isolation structures and doping the surrounding regions before subsequent thermal processing steps. The deep trenches act as pre-established barriers that prevent dopant diffusion into adjacent transistor regions during thermal processing, eliminating the need for increased lateral separation distances while maintaining ease of manufacture.
Solution Approach 2:
The patent introduces doped semiconductor regions as intermediary zones between adjacent transistors. These intermediary doped regions, formed within the deep trench isolation structures, serve as dopant sinks that absorb excess dopants during thermal processing, preventing lateral dopant spread into active transistor areas while allowing standard thermal processing conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the minimum lateral spacing between adjacent LDMOS transistors by 26-88%, allowing for a more compact arrangement and efficient use of silicon space while maintaining effective electrical isolation.
Implementation Method 1
significantly reducing the lateral diffusion of dopants
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
The density of a transistor array (300) is increased by forming one or more deep trench isolation structures (312, 314) in a semiconductor material (114). The deep trench isolation structures (312, 314) laterally surround transistors in the array (300). The deep trench isolation structures (312, 314) limit the lateral diffusion of dopants and the lateral movement of charge carriers.