Deep Trench Isolation Layout for Mixed Gate Height Semiconductors
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Solution Overview
Problem
The implementation of deep trench isolation in semiconductor devices often requires complex processes and multiple masks due to variations in gate structure heights, complicating the manufacturing process.
Innovation Solution
A semiconductor device design featuring a deep trench isolation structure with a planarized gap-fill insulating layer coplanar with a hard mask, a capping insulating layer, and varying thicknesses of hard mask layers to accommodate different gate structure heights, along with contact plugs penetrating these layers, to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench isolation is implemented with conventional methods, then electrical isolation between devices is achieved, but the manufacturing process becomes complicated requiring many masks and complex procedures
Solution Approach 1:
The patent applies preliminary action by forming the hard mask layer before creating the trench isolation structure. The hard mask layer is deposited and patterned in advance, then used as a template to define the trench isolation regions. This preliminary positioning of the hard mask eliminates the need for separate masking steps during trench formation, thereby simplifying the manufacturing process while maintaining electrical isolation reliability
Solution Approach 2:
The hard mask layer serves multiple functions: it acts as a pattern definition layer for trench isolation, as an etch stop layer, and as a reference structure for subsequent processing steps. By making the hard mask multi-functional, the patent reduces the number of separate layers and masks needed, thereby reducing manufacturing complexity while ensuring proper electrical isolation
2Adaptability or versatility
If gate structure heights are varied to accommodate different device requirements, then device functionality is improved, but the manufacturing process becomes more complicated
Solution Approach 1:
The patent applies local quality by having the hard mask layer with spatially varying thickness - thicker in some regions and thinner in others - corresponding to different gate structure heights. This local variation in hard mask thickness allows different device regions to have appropriate isolation depths without requiring separate processing sequences, thereby maintaining device functionality adaptability while simplifying the overall manufacturing process
Solution Approach 2:
The patent changes the thickness parameter of the hard mask layer to accommodate different gate heights. By controlling the hard mask thickness locally, the patent enables varied device functionalities (such as different transistor threshold voltages or channel lengths) without introducing additional complex processing steps, thus resolving the contradiction between adaptability and manufacturing complexity
3Reliability
If conventional trench filling methods are used, then trench isolation is formed, but chip area increases and manufacturing efficiency decreases
Solution Approach 1:
The patent applies self-service by using the hard mask layer itself as the filling material for the trench isolation. Instead of depositing separate fill materials and then performing planarization, the hard mask material is directly deposited into the trenches, self-aligning with the existing hard mask pattern. This self-service approach eliminates additional deposition and planarization steps, improving manufacturing efficiency while ensuring proper trench isolation formation
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.