Deep Trench Isolation Structure for Higher LDMOS Isolation Breakdown
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Solution Overview
Problem
The existing BCD process with deep trench isolation technology faces limitations in increasing the isolation breakdown voltage (ISO BV) of LDMOS devices, which is crucial for high voltage and high current applications, while also aiming to minimize specific on resistance (Rsp) and device size.
Innovation Solution
The semiconductor device incorporates a P-type lightly doped semiconductor layer, an undoped silicon layer, and N-type highly doped buried layers with deep trench isolations, where the undoped silicon layer surrounds the trench isolations and has a greater thickness than the buried layers, forming PN junctions closer to the trench bottoms, and includes a P-type epi-layer and channel stop regions to enhance breakdown voltage and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If deep trench isolation (DTI) is applied to BCD technology to reduce chip size, then device size is minimized, but isolation breakdown voltage cannot be sufficiently increased
Solution Approach 1:
The device is segmented into multiple functional layers: P-type lightly doped semiconductor layer, undoped silicon layer, N-type highly doped buried layer, and P-type epi-layer. This segmentation allows each layer to contribute specifically to either size reduction or breakdown voltage enhancement, resolving the contradiction between compact chip size and high isolation breakdown voltage
Solution Approach 2:
Different regions of the semiconductor structure are doped with different concentrations and types (P-type lightly doped, undoped, N-type highly doped) to create localized electrical properties. The undoped silicon layer specifically positioned between deep trench isolations provides localized high breakdown voltage, while maintaining overall small device footprint
2Productivity
If LDMOS device size is reduced to increase the number of dies on the wafer, then productivity increases, but breakdown voltage becomes difficult to maximize
Solution Approach 1:
The solution moves from planar scaling to vertical stacking by introducing multiple layers (undoped silicon layer, N-type buried layer, P-type epi-layer) in the vertical dimension. This allows breakdown voltage to be enhanced through vertical layer configuration rather than increasing horizontal device area, enabling higher productivity with maintained or improved breakdown voltage
3Ease of operation
If specific on resistance (Rsp) is minimized to improve power device performance, then ease of operation improves, but isolation breakdown voltage increases are limited
Solution Approach 1:
The doping concentration parameters are precisely controlled and changed across different layers: P-type lightly doped (1E16-1E18 atoms/cm³), undoped (intrinsic), N-type highly doped (1E19-1E21 atoms/cm³), and P-type epi-layer (1E15-1E17 atoms/cm³). This parameter optimization allows simultaneous achievement of low specific on resistance and high isolation breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes and increases the isolation breakdown voltage (ISO BV) beyond operational voltages, improving reliability under harsh switching conditions and reducing the dependency on process variability, resulting in higher breakdown voltages and more uniform electric field distribution.
Implementation Method 1
A first PN junction may be formed by the P-type lightly doped semiconductor layer and the first N-type highly doped buried layer, and the first PN junction may be formed in the undoped silicon layer
Implementation Method 2
the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer
Implementation Method 3
a channel stop region formed under the first and second deep trench isolations and disposed in the undoped silicon layer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate comprising a P-type lightly doped semiconductor layer; an undoped silicon layer formed on the P-type lightly doped semiconductor layer; a first deep trench isolation and a second deep trench isolation formed from an upper surface of the semiconductor substrate to the undoped silicon layer and filled with insulating films; and a first N-type highly doped buried layer formed on the undoped silicon layer, and disposed between the first deep trench isolation and the second deep trench isolation, wherein the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer.