Deep Trench Isolation Layout for Junction Leakage Reduction

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Solution Overview

Problem

Embedded flash integrated circuits in wearable devices experience significant leakage current, leading to increased power consumption and reduced standby time, necessitating a solution to minimize leakage current in small and concentrated integrated circuits.

Innovation Solution

Implementing a semiconductor structure with a deep trench isolation (DTI) below shallow trench isolation (STI) between adjacent well regions of different conductive types, which lengthens the path of leakage current and reduces its flow, while utilizing a tilting ion implantation process to minimize crystal defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If embedded flash integrated circuit is used to minimize device size, then device size is reduced, but leakage current increases leading to higher power consumption

Engineering Contradiction:
Improvedevice sizeVSAvoidpower consumption
Core Design Contradiction:
Volume of moving objectVSLoss of energy

Solution Approach 1:

The patent introduces a deep trench isolation structure that extends vertically into the substrate, adding a depth dimension to the isolation approach. This vertical extension creates a longer leakage current path without increasing lateral device dimensions, thereby reducing power consumption while maintaining compact device size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The deep trench isolation structure acts as an intermediary element between adjacent well regions of different conductive types. This intermediate structure blocks leakage current paths while allowing the integrated circuit to maintain its compact embedded flash design, effectively mediating between the need for small size and low power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If deep trench isolation is implemented between adjacent well regions, then leakage current path is lengthened and leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidstructure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The isolation structure is segmented into two distinct parts: a shallow trench isolation at the upper level and a deep trench isolation extending deeper into the substrate. This segmentation allows each trench to serve a specific function - the shallow trench provides basic isolation while the deep trench specifically targets leakage current reduction, making the overall solution more manageable despite increased complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shallow trench isolation is positioned above and partially overlaps with the deep trench isolation, creating a nested configuration. This nesting approach allows the shallower structure to be integrated with the deeper structure, sharing some process steps and reducing the overall manufacturing complexity compared to completely separate isolation structures.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor structure effectively reduces leakage current, thereby decreasing power consumption and improving reading/writing performance in memory integrated circuits by minimizing read/write errors.

Implementation Method 1

utilizing a tilting ion implantation process to minimize crystal defects

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20250329577A1Semiconductor structure with junction leakage reduction
Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250329577A1 patent drawing
  • US20250329577A1 patent drawing
  • US20250329577A1 patent drawing

AI summary

A method includes forming a well region in a substrate; forming a first implant region in the substrate, the first implant region; forming a second implant region in the well region; forming a first shallow trench isolation (STI) region in the substrate; forming first deep trench isolation (DTI) regions extending downwards from the first STI region into the well region; forming a second STI region in the substrate; forming second DTI regions extending downwards from the second STI region; forming a third STI region in the substrate; forming third DTI regions extending downwards from the third STI region; forming a gate electrode; forming a first source/drain region in the first implant region and in contact with the third STI region; and forming second source/drain region in the second implant region and between the first STI region and the second STI region.