Deep Trench Isolation for Reduced Area Power Devices
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Solution Overview
Problem
The existing deep trench isolation structures in integrated circuits often result in insufficient contact area between the deep well and the lower buried layer, which hinders the ability to maintain a desired bias, due to their proximity to the upper buried layer, leading to inadequate current supply for electrical isolation of transistors.
Innovation Solution
Increasing the lateral separation between the deep trench isolation structure and the upper buried layer by at least one micron on one end of the transistor, thereby expanding the contact area between the deep well and the lower buried layer, ensures sufficient current supply for maintaining the desired bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the deep trench isolation structure is placed close to the upper buried layer to reduce device area, then the device area is reduced, but the contact area between the deep well and lower buried layer becomes insufficient
Solution Approach 1:
The patent applies local quality by creating different separation distances at different locations: the deep trench isolation is separated from the upper buried layer by at least one micron on one end of the transistor (providing large contact area), while maintaining closer proximity on other ends (reducing overall device area). This localized variation in spacing resolves the contradiction between minimizing device area and maximizing contact area for bias maintenance.
2Area of moving object
If the deep trench isolation structure is placed close to the upper buried layer, then the device area is reduced, but the current supply for maintaining desired bias becomes inadequate
Solution Approach 1:
The patent ensures adequate current supply by locally increasing the contact area between the deep well and lower buried layer through greater separation from the upper buried layer on one end. This localized expansion of the contact region allows sufficient current flow to maintain the desired bias on the lower buried layer, while the overall device area remains minimized through closer spacing on other portions of the structure.
Data Source
AI summary
An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.