Deep Trench Isolation Profile for High-Voltage Breakdown Control
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Solution Overview
Problem
Current deep trench isolation (DTI) structures in integrated chips face challenges in maintaining effective electrical isolation as the insulator liner thickness reduces during removal processes, leading to breakdown under high voltage biases, especially when semiconductor devices operate at voltages greater than 100 Volts.
Innovation Solution
The method involves forming a DTI structure with an insulator liner that has varying thicknesses and protrusions, ensuring the liner remains thick enough to withstand high voltage biases by using an isotropic etch process to maintain the liner's integrity and coupling it with a shallow trench isolation (STI) structure, which extends through the active layer and into the base layer of a silicon-on-insulator (SOI) substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the insulator liner thickness is reduced to minimize area occupation, then the area of the IC is reduced, but the breakdown voltage capability deteriorates leading to isolation failure under high voltage biases
Solution Approach 1:
The insulator liner is designed with non-uniform thickness, featuring protrusions at critical locations where high voltage stress occurs. This local thickening provides enhanced breakdown voltage capability precisely where needed, while maintaining thinner sections in other areas to minimize overall IC area occupation.
Solution Approach 2:
The isolation structure extends vertically into deep trenches, utilizing the third dimension (depth) to provide adequate isolation performance. By increasing the vertical extent of the DTI structure rather than expanding laterally, the patent achieves reliable high-voltage isolation without proportionally increasing the horizontal IC area.
2Ease of manufacture
If the insulator liner thickness is reduced for area efficiency, then manufacturing cost is reduced, but device performance deteriorates due to leakage and breakdown
Solution Approach 1:
The insulator liner incorporates localized thickness variations with protrusions positioned at specific critical regions. This approach maintains manufacturing simplicity by using standard deposition and etching processes, while achieving enhanced isolation performance only where high voltage stress occurs, avoiding the need for uniformly thick liners throughout.
Solution Approach 2:
The patent modifies the geometric parameters of the insulator liner by introducing controlled thickness variations and protrusions. These parameter changes are achieved through adjusted etching conditions and deposition sequences, maintaining ease of manufacture while significantly improving breakdown voltage capability and preventing leakage in high-voltage regions.
3Reliability
If the DTI structure is designed with sufficient insulator liner thickness for high voltage isolation, then breakdown voltage is improved, but the area occupied on the IC increases
Solution Approach 1:
Rather than uniformly increasing insulator liner thickness across the entire structure, the patent applies localized thickening only at protrusions positioned at critical high-stress regions. This provides sufficient breakdown voltage capability where needed while minimizing the overall area occupied by the DTI structure on the IC.
Solution Approach 2:
The patent shifts the isolation strategy from lateral expansion to vertical extension, creating deep trenches with insulator liners that extend significantly in depth rather than width. This three-dimensional approach achieves adequate breakdown voltage capability without proportionally increasing the horizontal IC area occupation.
Data Source
AI summary
In some embodiments, the present disclosure relates to a method that includes forming a shallow trench isolation (STI) structure that extends into a substrate. A masking layer is formed over the substrate and includes an opening overlying the STI structure. A first removal process removes portions of the STI structure underlying the opening of the STI structure. A second removal process laterally removes portions of the substrate below the STI structure. A third removal process removes portions of the substrate that directly underlie the opening of the masking layer. An insulator liner layer is formed within inner surfaces of the substrate as defined by the first, second, and third removal processes. Further, a fourth removal process removes portions of the insulator liner layer covering a lower surface of the substrate. A semiconductor material is then formed over the SOI substrate and on the insulator liner layer.