Deep Trench Isolation for Shared Back Gate Logic Cells
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Solution Overview
Problem
Field-effect transistors fabricated using silicon-on-insulator technologies face challenges with switching delay and standby leakage when operating in fully-depleted mode, and dual-gate dynamic switching is not achievable due to the inability to share back gates between transistors in logic cells.
Innovation Solution
A structure is developed with a shared back gate for two field-effect transistors, surrounded by deep trench isolation regions and a dielectric layer, allowing for dual-gate switching and reducing propagation delay and standby leakage by physically and electrically isolating the back gate from other wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field-effect transistors are operated in fully-depleted mode in silicon-on-insulator technology, then device performance is improved, but switching delay and standby leakage increase
Solution Approach 1:
The patent divides the back gate control into separate segments for different logic cells by introducing deep trench isolation regions. These isolations physically separate the back gate wells of adjacent logic cells, allowing independent back gate voltage control while maintaining the fully-depleted mode operation benefits for each cell individually, thereby reducing unwanted coupling effects that cause switching delay and standby leakage.
2Reliability
If field-effect transistors are operated in fully-depleted mode in silicon-on-insulator technology, then device performance is improved, but standby leakage increases
Solution Approach 1:
The deep trench isolation regions segment the substrate into electrically isolated regions, preventing leakage current paths between adjacent logic cells. This segmentation allows each logic cell to maintain optimal fully-depleted operation while minimizing standby leakage through physical isolation of the back gate wells.
3Adaptability or versatility
If back gates are shared between field-effect transistors in logic cells, then dual-gate dynamic switching is achieved, but isolation between logic cells becomes difficult
Solution Approach 1:
The patent applies segmentation by introducing deep trench isolation regions that physically divide the substrate into isolated logic cell regions. This allows back gate wells to be shared within a logic cell for dual-gate switching while simultaneously providing electrical isolation between adjacent logic cells, resolving the contradiction between sharing and isolation.
Solution Approach 2:
The deep trench isolation regions act as intermediary elements between adjacent logic cells. These isolations mediate the conflict between back gate sharing (which requires connectivity) and logic cell isolation (which requires separation) by providing electrical insulation while allowing the back gate voltage to be controlled for dual-gate switching within each isolated cell.
4Reliability
If deep trench isolation regions are introduced to isolate logic cells, then isolation is improved, but device complexity increases
Solution Approach 1:
The patent uses segmentation through deep trench isolation regions to achieve reliable logic cell isolation. While this does increase fabrication complexity, the segmentation approach provides a systematic and scalable solution that can be integrated into existing CMOS fabrication processes, making the complexity increase manageable and justified by the significant improvements in logic cell isolation and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shared back gate enables dual-gate switching, reducing both propagation delay and standby leakage in logic cells, enhancing the performance of field-effect transistors in fully-depleted silicon-on-insulator technology.
Implementation Method 1
A dielectric layer is arranged between the well and the logic cell, and a plurality of deep trench isolation regions extend through the dielectric layer
Data Source
AI summary
Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.