Deep Trench Isolation Structure for Reliable SOI Power Semiconductors
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Solution Overview
Problem
High power semiconductor devices require enhanced reliability to meet stringent safety standards in industrial and aviation applications, while manufacturing costs and processes need to be optimized to maintain efficiency without significant changes.
Innovation Solution
A method for manufacturing a semiconductor isolation structure involving the formation of a silicon-on-insulation wafer with shallow and deep trench isolation structures, using techniques like plasma dry etching and chemical mechanical planarization, to create a reliable and efficient semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench isolation structures are formed to enhance reliability, then device reliability improves, but manufacturing complexity increases
Solution Approach 1:
The isolation structure is divided into multiple segments: a first isolation structure with a first depth and a second isolation structure with a second depth greater than the first depth. This segmentation allows different regions to have different isolation characteristics, enhancing overall device reliability while managing manufacturing complexity through modular construction
Solution Approach 2:
The patent introduces depth as a critical dimension by forming isolation structures at different depths within the semiconductor substrate. The first isolation structure is formed at a shallower depth while the second isolation structure extends deeper, creating a multi-level isolation architecture that improves reliability without requiring complete redesign of the manufacturing process
2Productivity
If existing manufacturing processes are maintained without significant changes, then manufacturing efficiency is preserved, but device reliability may be insufficient
Solution Approach 1:
The method performs preliminary actions by first forming the shallower first isolation structure, then subsequently forming the deeper second isolation structure. This sequential approach allows each isolation level to be optimized independently while maintaining compatibility with existing manufacturing processes, ensuring both reliability improvement and manufacturing efficiency
Solution Approach 2:
The patent changes the depth parameter of isolation structures by forming a second isolation structure with a greater depth than the first isolation structure. This parameter modification enhances the isolation effectiveness and device reliability while using standard manufacturing techniques, thus maintaining manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability of high power semiconductor devices by providing effective insulation and electrical connectivity, improving manufacturing efficiency without altering existing processes significantly.
Implementation Method 1
using techniques like plasma dry etching and chemical mechanical planarization
Implementation Method 2
using techniques like plasma dry etching and chemical mechanical planarization
Data Source
AI summary
A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.