Deep Trench Selective Epitaxy at Low Temperature for MOL Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in integrating low temperature epitaxy to reduce contact resistance in nMOS transistors while preserving the high-K metal gate stack, particularly in the middle-of-line (MOL) fabrication process.
Innovation Solution
A cluster tool and method for forming epitaxial layers using a transfer chamber, pre-clean chamber, plasma-cleaning chamber, deposition chamber, etch chamber, and thermal process chamber, with specific cleaning and deposition processes to form silicon-containing films at low temperatures, including plasma-based oxide etch, epitaxial deposition, and etch-back techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low temperature epitaxy is used to reduce contact resistance, then dopant activation is improved, but the thermal budget constraint threatens to damage the high-K metal gate stack
Solution Approach 1:
The patent changes the temperature parameter from conventional high temperature (above 450°C) to low temperature (below 450°C, specifically 200-400°C) epitaxial growth conditions. This parameter change enables high dopant activation while preserving the high-K metal gate stack, as the lower temperature prevents thermal damage to the gate structure while still providing sufficient energy for dopant incorporation and activation in the silicon layer.
Solution Approach 2:
The patent performs preliminary cleaning and preparation steps (oxide removal, surface treatment) before the low temperature epitaxial growth. These preliminary actions ensure the substrate surface is properly prepared for low temperature silicon deposition, enabling successful epitaxial growth and high dopant activation even at temperatures below 450°C where conventional growth would fail.
2Quantity of substance
If conventional high temperature epitaxy is used, then silicon layer growth is achieved, but contact resistance remains high due to insufficient dopant activation
Solution Approach 1:
The patent changes multiple parameters simultaneously: temperature (reduced to 200-400°C), pressure (controlled at specific values), and gas composition (using phosphine or other phosphorous-containing gases). These parameter changes enable the silicon layer to grow with high dopant activation, achieving low contact resistance while maintaining proper film quality and crystalline structure.
Solution Approach 2:
The patent creates a composite structure by incorporating phosphorous dopants directly into the silicon layer during low temperature epitaxial growth. This results in a phosphorous-doped silicon layer that combines the electrical conductivity benefits of doping with the structural integrity of epitaxial silicon, achieving both good film growth and low contact resistance.
3Reliability
If low temperature epitaxy is implemented, then contact resistance is reduced, but process integration complexity increases due to additional cleaning and deposition steps
Solution Approach 1:
The patent merges multiple functions into the low temperature epitaxial growth process itself. The same process step that deposits the silicon layer also simultaneously dopes it with phosphorous, achieving both film formation and dopant incorporation in a single step. This reduces the number of separate process steps needed compared to conventional approaches requiring separate deposition and doping steps.
Solution Approach 2:
The low temperature epitaxial growth process serves multiple functions: it removes residual oxides, deposits the silicon layer, incorporates phosphorous dopants, and activates the dopants all in one process step. This multi-functionality simplifies process integration despite the lower temperature constraints, as the single process achieves what would otherwise require multiple separate steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables high dopant activation in epitaxial films, reducing contact resistance and maintaining the integrity of the high-K metal gate stack by achieving selective growth and etching of silicon-containing layers at temperatures below 450°C.
Implementation Method 1
a first cleaning chamber coupled to the transfer chamber, the first cleaning chamber comprising a capacitively coupled plasma source
Implementation Method 2
an epitaxial deposition chamber coupled to the transfer chamber, the epitaxy chamber comprising a liquid vaporizer in fluid communication with a liquid precursor source
Implementation Method 3
methods of depositing silicon-containing films for forming semiconductor devices
Data Source
AI summary
Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.