Deep Trench Memory Cell With Collar Oxide And Buried Strap
Solution Overview
Problem
Conventional semiconductor memory devices face device failure due to insufficient distance between adjacent memory units, which is exacerbated by the shrinkage of device size, affecting data storage time and process window.
Innovation Solution
The semiconductor memory device fabrication process involves forming deep trenches with a collar oxide layer and buried conductive layers, allowing for a larger trench size while maintaining electrical connectivity between memory units through strategically placed buried straps and conductive layers, thereby increasing the distance between units and reducing failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent memory units is reduced to increase device density, then device density is improved, but device reliability deteriorates due to increased risk of device failure
Solution Approach 1:
The patent introduces a vertical dimension by forming deep trenches (extending downward from the substrate surface) to accommodate capacitors, rather than placing all components in the planar horizontal plane. This allows memory units to be stacked vertically, increasing device density without reducing the horizontal distance between adjacent units, thus maintaining reliability while improving productivity.
Solution Approach 2:
The patent nests the capacitor structure within the deep trench, which itself is nested within the semiconductor substrate. The collar oxide layer is nested on the sidewalls of the deep trench, and the conductive layers are nested within the trench. This nested arrangement compactly packages multiple components in a vertical stack, achieving high density without compromising the spacing between adjacent memory units.
2Reliability
If the deep trench size is reduced to increase the distance between adjacent memory units, then device reliability is improved, but data storage time deteriorates
Solution Approach 1:
The patent changes the geometric parameters of the capacitor structure by forming deep trenches with controlled depth and width ratios. The collar oxide layer thickness and the conductive layer dimensions are also optimized. These parameter adjustments allow the capacitor to maintain sufficient storage capacity (data storage time) even in a compact deep trench structure that provides adequate spacing between adjacent memory units for reliability.
3Length of stationary object
If the deep trench size is reduced to increase the distance between adjacent memory units, then the distance between units is improved, but process window deteriorates
Solution Approach 1:
The patent applies preliminary protective actions by forming the collar oxide layer on the sidewalls of the deep trench before filling the trench with capacitor structures. This collar structure serves as a pre-formed protective barrier and alignment reference that simplifies subsequent processing steps. The isolation structures are also formed in advance to prevent shorts, providing a robust process window that tolerates variations in trench dimensions while maintaining adequate spacing between units.
Data Source
AI summary
A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the deep trench. The top of the first sidewall is at the same height as the surface of the semiconductor substrate. The top of the second sidewall is substantially equal to the top of the capacitor. The memory cell further comprises a buried conductor layer disposed on the second sidewall and the capacitor and a buried strap adjoining the buried conductive layer, and a transistor disposed on the surface of the semiconductor substrate and electrically connected to the capacitor through the buried strap and the buried conductive layer.