Deep Trench MIM Capacitor Layout to Eliminate Barrier Layer Overhang
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Solution Overview
Problem
Complementary metal-oxide semiconductor (CMOS) image sensors face challenges in achieving high capacitance for integrated circuits (ICs) due to the barrier layer overhang issue in deep trench MIM capacitors, which affects capacitance and increases manufacturing costs and resistance, particularly with physical vapor deposition (PVD) and atomic layer deposition (ALD) methods.
Innovation Solution
The barrier layer is formed first and then the capacitor trench is created to expose a portion of the barrier layer, allowing more space for the MIM capacitor, and the barrier layer is formed outside the trench to prevent overhang, using physical vapor deposition (PVD) to reduce resistance and enhance wafer per hour (WPH) and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the barrier layer is formed before the capacitor trench using PVD, then resistance is reduced and manufacturing cost decreases, but barrier layer overhang occurs in deep trenches affecting capacitance
Solution Approach 1:
The barrier layer is formed in advance before the capacitor trench is etched, allowing the barrier material to be deposited on the substrate surface prior to trench formation. This preliminary action enables better control of barrier layer thickness and composition, and prevents overhang by establishing the barrier layer boundary before the trench geometry is created.
Solution Approach 2:
The conventional sequence of forming the barrier layer after the capacitor trench is inverted. Instead of following the traditional approach where the trench is etched first and then the barrier layer is deposited (which causes overhang), the barrier layer is formed first and then the trench is etched through it, eliminating the overhang problem while maintaining low resistance through PVD deposition.
2Productivity
If physical vapor deposition (PVD) is used to form the barrier layer, then resistance is reduced and wafer per hour increases, but barrier layer overhang affects capacitance in deep trenches
Solution Approach 1:
The barrier layer is deposited using PVD as a preliminary step before trench etching. This allows the high-speed PVD process to be utilized effectively, achieving low resistance and high wafer throughput, while the subsequent trench etching process removes the overhang issue by defining the trench geometry after the barrier layer is already in place.
Solution Approach 2:
The process sequence is inverted from the conventional approach: instead of etching the trench first and then depositing the barrier layer (which causes overhang and requires slower ALD processes), the barrier layer is deposited first using fast PVD, then the trench is etched. This inversion maintains both high productivity and reliability.
3Reliability
If the barrier layer is formed outside the trench, then overhang is prevented and capacitance increases, but manufacturing process complexity increases
Solution Approach 1:
The barrier layer is formed as a preliminary layer across the entire substrate surface before the capacitor trench is etched. This preliminary formation ensures the barrier layer extends beyond where the trench will be, and the subsequent trench etching naturally creates the 'outside the trench' configuration without requiring additional patterning or deposition steps, thus avoiding increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the capacitance of MIM capacitors, reduces resistance, and improves the performance of ICs by eliminating the barrier layer overhang issue and lowering the RC delay, while maintaining lower costs and faster processing times.
Implementation Method 1
using physical vapor deposition (PVD) to reduce resistance and enhance wafer per hour (WPH) and cost
Data Source
AI summary
Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.