Deep Trench Isolation Structure With Multiple Voids for Crack Resistance
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Solution Overview
Problem
Conventional high voltage semiconductor devices with deep trench isolation regions are prone to cracks due to stress concentration at single voids, leading to defects and deterioration of breakdown voltage characteristics.
Innovation Solution
The proposed high voltage semiconductor device features multiple voids spaced apart in the isolation region, with a trench design where the inner sidewalls' width decreases downward and scallops are formed, allowing for gap-filling with insulating layers to create multiple voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single void is formed in the deep trench isolation region, then the isolation structure is simple to manufacture, but stress concentrates at the void leading to cracks and device defects
Solution Approach 1:
The single void in the isolation region is segmented into multiple smaller voids arranged in an array. This segmentation distributes the stress that would otherwise concentrate at a single void location, preventing crack formation while maintaining the electrical isolation function. The multiple voids are formed by creating a patterned mask layer with multiple openings over the trench region, then filling with insulating material to create the void array structure.
2Reliability
If multiple voids are formed in the isolation region to distribute stress, then crack resistance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The mask layer pattern is designed and formed in advance before the insulating material filling process. This preliminary action defines the positions and dimensions of multiple voids beforehand, allowing the subsequent filling process to create the complete array of voids in a single operation. The mask layer serves as a template that guides the formation of all voids simultaneously, reducing process complexity despite the multi-void structure.
3Reliability
If cracks occur in the isolation region above a void, then tungsten can penetrate into the crack space during contact process, but this penetration is prevented by the multiple void configuration
Solution Approach 1:
The multiple voids are positioned and sized to act as stress-distributing elements before cracks can form. By distributing stress across multiple void interfaces rather than concentrating it at one location, the structure prevents the initiation of cracks that would otherwise propagate upward through the isolation region. This beforehand cushioning effect eliminates the pathway for tungsten penetration during subsequent contact processes, protecting the breakdown voltage characteristics.
Data Source
AI summary
A high voltage semiconductor device includes an isolation region, in which multiple voids are formed in the isolation region along the vertical direction of the isolation region, so that the possibility of cracks occurring in the isolation region is minimized, and thus tungsten (W), etc. is prevented from penetrating into a space created by the cracks in a subsequent process and deteriorating the breakdown voltage characteristics.