Deep Trench Isolated NMOS Biasing for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing isolated NMOS transistors in communication devices suffer from decreased gain due to parasitic capacitance introduced by deep trench components, leading to incorrect signal interpretation and degraded Signal-to-Noise Ratio (SnR) in OOK signal detection.
Innovation Solution
Implementing a resistor that connects the isolated region within the deep trench components to a supply voltage, reducing effective capacitance at the source terminal and improving gain by charging parasitic capacitors from two nodes, and connecting the input terminal to both the source node and isolated layer of the DT region for further gain enhancement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench components are used for galvanic isolation, then isolation performance is improved, but parasitic capacitance increases causing gain degradation
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by introducing a resistor that disconnects the isolated region from the supply voltage terminal during signal detection. This removes the capacitive coupling path between the deep trench isolation structure and the transistor source terminal, eliminating the gain degradation caused by parasitic capacitance while maintaining galvanic isolation when needed.
Solution Approach 2:
The patent implements a dynamic configuration where the isolation terminal is selectively connected to either the supply voltage terminal or left floating based on operational requirements. During OOK signal detection, the isolation terminal is left floating to minimize parasitic capacitance impact on gain, while maintaining isolation performance when galvanic separation is required.
2Reliability
If isolation terminal is connected to supply voltage, then isolation is maintained, but capacitance at source terminal increases reducing gain
Solution Approach 1:
The patent removes the direct capacitive coupling between the isolation terminal and supply voltage by introducing a resistor in series. This extraction of the harmful capacitive path allows the isolation terminal to be connected to supply voltage for isolation maintenance without significantly increasing capacitance at the source terminal, thereby preserving transistor gain.
3Object-generated harmful factors
If resistor is added to connect isolation region to supply voltage, then parasitic capacitance is reduced and gain is improved, but device complexity increases
Solution Approach 1:
The patent introduces a resistor as an intermediary element between the isolation terminal and supply voltage terminal. This single passive component serves as a mediator that blocks capacitive coupling while allowing DC voltage connection, reducing parasitic capacitance and improving gain without significantly increasing device complexity.
4Measurement precision
If input terminal is connected to both source node and isolated layer, then gain is enhanced for signal detection, but device complexity increases
Solution Approach 1:
The patent makes the input terminal multi-functional by connecting it to both the source node and the isolated layer of the deep trench region. This single input terminal serves dual purposes: receiving the OOK signal through the source node and detecting signal-induced voltage changes on the isolated layer, thereby enhancing detection accuracy without adding separate detection circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution increases the gain of detector circuitry, enhancing Signal-to-Noise Ratio (SnR) and improving the accuracy of OOK signal detection by ensuring timely changes in the VOUT signal, thus maintaining accurate data transmission.
Implementation Method 1
reducing effective capacitance at the source terminal
Data Source
AI summary
An example apparatus includes: a first resistor having a first terminal coupled to a supply voltage terminal and a second terminal; a transistor having a gate terminal coupled to a first input terminal, a source terminal coupled to a second input terminal, a body terminal coupled to the source terminal, and a drain terminal coupled to the second terminal of the first resistor; a substrate terminal coupled to ground; an isolation terminal that separates the transistor from the substrate terminal; a second resistor having a first terminal coupled to the isolation terminal and a second terminal coupled to the supply voltage terminal; and a third resistor having a first terminal coupled to the source terminal of the transistor and a second terminal coupled to ground.