Deep Trench Resistor Structure for Pseudo-Zero TCR Stability

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Solution Overview

Problem

Integrated passive devices (IPDs) face challenges in achieving resistance that is not temperature-dependent, as existing resistor structures in semiconductor substrates exhibit varying resistance with temperature changes, affecting device performance and efficiency.

Innovation Solution

A deep trench resistor (DTR) structure is developed with layers having positive and negative temperature coefficients of resistance (TCR), combined with a tunable device to maintain constant resistance by adjusting the resistance of specific segments through the tunable device, thereby reducing temperature dependency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing resistor structures are used in semiconductor substrates, then device integration is achieved, but resistance becomes temperature-dependent affecting device performance

Engineering Contradiction:

Improvedevice performanceVSAvoidtemperature dependency of resistance

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The resistor structure is divided into multiple segments with different materials having opposite temperature coefficients of resistance (positive TCR and negative TCR). Each segment contributes differently to the overall resistance temperature characteristic, allowing the temperature dependencies to compensate for each other and achieve pseudo-zero TCR performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs composite material structures combining different resistive materials with contrasting temperature coefficients. By integrating materials with positive TCR (e.g., certain metal alloys) and negative TCR (e.g., certain metal nitrides or oxides) in a single resistor structure, the temperature-dependent resistance variations are balanced to achieve temperature-stable resistance.

Inventive Principle:

Principle #40Composite materials

2Temperature

If deep trench resistor structure with multiple layers is implemented, then pseudo zero TCR performance is achieved, but device complexity increases

Engineering Contradiction:

Improvetemperature stability of resistanceVSAvoidresistor structure complexity

Core Design Contradiction:

TemperatureVSDevice complexity

Solution Approach 1:

The resistor is segmented into distinct functional layers within a deep trench structure, where each layer has a specific material composition and temperature coefficient characteristic. This segmentation allows independent optimization of each layer's resistance contribution while maintaining overall temperature stability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the resistor structure have locally optimized material properties - specific layers are designed with particular materials having predetermined positive or negative TCR values. This local quality differentiation enables precise control over the temperature-resistance relationship without requiring complex external control mechanisms.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The DTR structure achieves pseudo zero TCR performance by maintaining consistent resistance across varying temperatures, enhancing device stability and performance in semiconductor integrated circuits.

Implementation Method 1

Methodology Applied

Scientific EffectTemperature coefficient of resistance compensation:

Data Source

PatentUS20250366039A1Deep trench resistor structure and methods of forming the same

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.