Deep Trench Resistor Structure for Pseudo Zero TCR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated passive devices (IPDs) face challenges in achieving temperature-independent resistance due to the temperature-dependent resistance characteristics of deep trench resistors (DTRs) used in semiconductor substrates, which affect the performance and reliability of mobile devices and application processors.
Innovation Solution
A deep trench resistor (DTR) structure is developed, incorporating a first layer with a positive temperature coefficient of resistance (TCR) and a second layer with a negative TCR, along with a tunable device connected to the DTR to achieve pseudo zero TCR performance. The tunable device adjusts the resistance of the DTR by controlling the current flow through segments of the resistor, maintaining resistance constancy across varying temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a deep trench resistor is used in semiconductor substrates, then device integration and functional density are improved, but temperature-dependent resistance characteristics worsen, affecting performance reliability
Solution Approach 1:
The patent employs a composite resistor structure consisting of multiple layers with different temperature coefficients of resistance (TCR). Specifically, it combines a first resistor layer with positive TCR, a second resistor layer with negative TCR, and optionally a third resistor layer with positive TCR. These layers are stacked vertically within the deep trench structure, creating a composite material system where the opposing TCR characteristics compensate for each other, achieving near-zero overall TCR while maintaining the integration benefits of deep trench resistors.
2Reliability
If multiple layers with different TCR are combined, then temperature independence of resistance is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar resistor designs to a vertical three-dimensional stacked structure. Multiple resistor layers with different TCR characteristics are arranged in the vertical dimension within the deep trench, rather than spreading them out horizontally. This vertical stacking achieves temperature compensation while occupying minimal lateral space, thereby reducing overall device complexity and improving integration density.
Solution Approach 2:
The resistor function is segmented into multiple distinct layers, each with specific TCR characteristics. The first layer provides positive TCR, the second layer provides negative TCR, and the third layer (when present) provides additional positive TCR. Each layer is independently formed and controlled, allowing precise tuning of the overall temperature coefficient by adjusting individual layer properties, thus achieving temperature independence through functional segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DTR structure effectively reduces temperature dependency of resistance, ensuring consistent performance of IPDs across temperature variations, enhancing the reliability and efficiency of mobile devices and application processors.
Implementation Method 1
a first layer with a positive temperature coefficient of resistance (TCR) and a second layer with a negative TCR
Data Source
AI summary
A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.