Deep Trench Termination Layout for High-Voltage Breakdown Control
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Solution Overview
Problem
High voltage semiconductor devices face a trade-off between static breakdown voltage and substrate injection due to the need for reduced dopant concentration, leading to higher device substrate carrier injection and latch-up problems, particularly in automotive applications.
Innovation Solution
A semiconductor device with a termination region comprising a vertical path cell and deep trench termination cells with specific dopant concentrations and geometries to alleviate electric field crowding and improve voltage tolerance, including a first type deep trench termination cell with a first well region and a second type deep trench termination cell with a second well region, both electrically coupled to the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher breakdown voltage is required, then dopant concentration of P type substrate and N type buried layer is reduced, but substrate carrier injection and latch-up problems increase
Solution Approach 1:
The termination region is divided into multiple cell types (first type termination cells with deep trench isolation and second type termination cells without deep trench isolation). This segmentation allows different regions to have different dopant concentrations optimized for their specific functions, enabling high breakdown voltage while controlling substrate injection through selective deep trench isolation placement.
Solution Approach 2:
Deep trench isolation is selectively applied only in specific termination cells (first type) rather than uniformly across all termination regions. This local quality approach allows precise control of electric field distribution and substrate injection in critical areas while maintaining low on-resistance in other areas through appropriate dopant concentrations.
2Reliability
If deep trench isolation is used in termination region, then breakdown voltage and ruggedness are improved, but area occupied by termination region increases
Solution Approach 1:
The termination region uses a mixed configuration where only first type termination cells include deep trench isolation structures, while second type termination cells omit them. This selective segmentation reduces the total area occupied by deep trench isolation while maintaining breakdown voltage in critical regions where substrate injection control is most needed.
Solution Approach 2:
Instead of applying deep trench isolation to all termination cells (excessive action), the patent applies it only to first type termination cells (partial action). This partial application is sufficient to control substrate injection and maintain breakdown voltage while minimizing the area consumed by termination structures.
3Reliability
If dopant concentration is reduced to increase breakdown voltage, then static breakdown voltage is improved, but device substrate carrier injection increases
Solution Approach 1:
The patent implements local quality by creating termination cells with different structures: first type cells with deep trench isolation for substrate injection control, and second type cells without deep trench isolation for optimized electrical performance. This allows different dopant concentration profiles in different regions, enabling high breakdown voltage overall while controlling substrate injection locally where needed.
Solution Approach 2:
The deep trench isolation structure acts as an intermediary element between the high voltage terminal and the substrate. It provides a physical and electrical barrier that controls substrate carrier injection without requiring uniform reduction of dopant concentration across the entire device, thus maintaining breakdown voltage while preventing excessive substrate injection.
Data Source
AI summary
A semiconductor device having a termination region comprising deep trench isolation (“DTI”). The termination region may be formed in a semiconductor layer of a first conductivity type and may include a vertical path cell of a second conductivity type vertically extended into the semiconductor layer with a vertical path cell depth, a first type deep trench termination cell (“DTTC”) disposed laterally immediately next to the vertical path cell and including a first DTI and a first well region of the second conductivity type disposed laterally immediately next to the first DTI, and a second type DTTC having a second DTI disposed laterally immediately next to the first type DTTC, and a second well region of the first conductivity type disposed laterally immediately next to the second DTI.