Deep Trench Varactor With Parallel DC Path
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Solution Overview
Problem
Conventional semiconductor varactors face challenges in maintaining high Q factor and efficiency at the 22 nm node of CMOS technology due to increased process complexity and costs, particularly in embedded dynamic random access memory (eDRAM) and fin field effect transistor (FinFET) structures.
Innovation Solution
The semiconductor structure incorporates a deep trench varactor with a parallel DC path, featuring a conductive inner electrode insulated by a node dielectric and electrically coupled to the semiconductor region, allowing AC signals to pass through a highly conductive trench fill, reducing dynamic resistance and enhancing the Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional varactor structures are used at 22 nm node, then device functionality is maintained, but dynamic resistance increases and Q factor deteriorates
Solution Approach 1:
The varactor structure is segmented into distinct functional regions: a deep trench varactor region for capacitance function and a separate parallel DC path region for low-resistance current flow. This segmentation allows each region to be optimized independently, with the DC path providing a dedicated low-resistance route that bypasses the high-resistance varactor junction, thereby reducing overall dynamic resistance while maintaining the Q factor
Solution Approach 2:
An intermediary n-type connection region is introduced between the p-type substrate and the n-type varactor region. This intermediary region serves as a low-resistance current pathway that mediates the electrical connection, providing a parallel DC path that reduces dynamic resistance. The intermediary region acts as a bridge that allows high-frequency AC signals to pass through the varactor while providing a separate low-impedance path for DC current flow
2Reliability
If process elements are added to maintain varactor performance at 22 nm node, then Q factor can be maintained, but manufacturing complexity and cost increase
Solution Approach 1:
The n-type connection region serves multiple functions simultaneously: it provides a low-resistance DC current path to reduce dynamic resistance, acts as an electrical connection between the p-type substrate and n-type varactor region, and can be formed using standard CMOS fabrication processes. This multi-functionality eliminates the need for additional specialized process elements while achieving both low dynamic resistance and high Q factor
Solution Approach 2:
The invention changes the doping parameters and structural configuration of existing regions rather than introducing new process elements. By adjusting the doping concentration and depth of the n-type connection region, and by configuring the deep trench geometry, the patent achieves optimized electrical performance using standard fabrication processes, thereby maintaining Q factor without increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the Q factor by reducing dynamic resistance and enabling efficient AC signal passage, addressing the resistance issues in conventional varactors and maintaining high performance at advanced technology nodes.
Implementation Method 1
a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric
Implementation Method 2
A varactor is a solid-state diode the capacitance of which changes depending on a voltage applied thereto
Implementation Method 3
allowing AC signals to pass through a highly conductive trench fill, reducing dynamic resistance and enhancing the Q factor
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.