Deep Trench Capacitor Via Layout for Lower ESR and Higher AC Density
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Solution Overview
Problem
Conventional semiconductor devices face challenges in maximizing capacitance density and minimizing equivalent series resistance (ESR) in deep trench capacitors (DTCs) due to the design of via contacts, which affects signal stability and operating frequency.
Innovation Solution
The introduction of novel DTC designs with multiple via contacts connected to the top and bottom plates, shared via contacts between adjacent DTCs, and additional via contacts laterally surrounding DTCs to reduce ESR and increase AC capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via contact design is used in deep trench capacitors, then device complexity is reduced, but equivalent series resistance increases and AC capacitance density decreases
Solution Approach 1:
The via contact structure is segmented into multiple individual via contacts instead of a single via contact. Each via contact is connected to respective top and bottom plates of the deep trench capacitor, creating parallel current paths that reduce equivalent series resistance while maintaining signal stability.
Solution Approach 2:
Multiple via contacts are combined in parallel between the top and bottom plates of the deep trench capacitor. This merging of multiple conductive paths reduces the overall equivalent series resistance while increasing AC capacitance density, resolving the contradiction between reliability and device complexity.
2Reliability
If multiple via contacts are added to reduce ESR, then equivalent series resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The multiple via contacts are formed using preliminary patterning and etching steps that define all via contact locations before capacitor plate formation. This preliminary action allows subsequent filling and planarization steps to proceed efficiently, reducing manufacturing complexity despite the increased number of via contacts.
Solution Approach 2:
The via contacts serve multiple functions: providing electrical connection between top and bottom plates, reducing equivalent series resistance, and increasing AC capacitance density. This multi-functionality justifies the additional manufacturing steps while delivering multiple performance benefits simultaneously.
3Reliability
If via contacts are added laterally surrounding DTCs, then AC capacitance density increases, but device area increases
Solution Approach 1:
Via contacts are arranged in a three-dimensional configuration around the deep trench capacitor, utilizing vertical and lateral dimensions. This spatial arrangement increases AC capacitance density by optimizing the electromagnetic field distribution without proportionally increasing the planar package area.
Solution Approach 2:
The via contacts are nested around the deep trench capacitor structure, with inner via contacts closer to the capacitor and outer via contacts forming a surrounding pattern. This nested arrangement maximizes the use of available space while increasing AC capacitance density without linearly increasing package area.
Data Source
AI summary
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. In one aspect, the semiconductor device includes a plurality of deep trench capacitors and a plurality of via contacts that at least partially surround the deep trench capacitors. Variations may be made to the number and locations of the plurality of via contacts such that design requirements for the packaging are satisfied.