Deep Via Bar Isolation Layout for Lower-Resistance Backside Power
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and requires new methodologies to optimize performance and density.
Innovation Solution
The implementation of deep via bar isolation using poly cut processing, which eliminates the need for two immersion layers and a power plug process, enabling self-aligned fabrication and recessed deep via bar structures to reduce process complexity and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing compatibility and cost are maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node and below
Solution Approach 1:
The fabrication process is divided into distinct stages: forming isolation regions, forming via holes through the isolation regions, depositing conductive material in the via holes, and planarizing the surface. This segmentation allows each stage to be optimized independently, achieving high precision at 10nm node while managing overall process complexity.
Solution Approach 2:
Isolation regions are formed preliminary before transistor fabrication. This preliminary action establishes a stable foundation that enables subsequent precise patterning and fabrication steps, improving manufacturing precision while the standardized isolation process helps manage fabrication complexity.
2Productivity
If feature size is reduced to increase device density, then capacity increases, but process variability worsens and limits further scaling
Solution Approach 1:
The isolation regions provide localized electrical isolation with specific material properties (different dielectric constant from surrounding materials) tailored to control signal interference and power consumption. This local quality enhancement enables higher device density while maintaining signal integrity and reducing process variability through controlled electrical characteristics.
Solution Approach 2:
The patent modifies physical parameters including the dielectric constant of isolation materials, via hole dimensions, and conductive material properties. These parameter changes enable scaling to higher densities while controlling process variability through optimized electrical characteristics and reduced sensitivity to dimensional variations.
3Reliability
If deep via bar isolation is implemented, then power network resistance and capacitance are minimized, but process complexity increases
Solution Approach 1:
The via bars serve dual functions: providing electrical connection for power delivery and serving as isolation structures. This merging of functions reduces the need for separate isolation elements, thereby minimizing power network resistance and capacitance while avoiding proportional increases in structural complexity.
Solution Approach 2:
The deep via bars are designed to perform multiple functions simultaneously: electrical isolation, power delivery, and signal routing. This multi-functionality achieves minimized power network resistance and capacitance without proportionally increasing process complexity, as the same structures serve multiple purposes in the power network.
4Ease of manufacture
If immersion layers are removed to simplify process, then manufacturing precision may be affected, but ease of manufacture improves
Solution Approach 1:
The fabrication process utilizes self-aligned techniques where previously formed structures serve as alignment references for subsequent steps. For example, isolation region boundaries automatically define via hole positions, eliminating the need for separate alignment operations and maintaining precision without requiring immersion layers.
Data Source
AI summary
Integrated circuit structures having deep via bar isolation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes has a cut between first and second conductive structure portions. A cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.