Deep Via Bar Width Tuning for Lower-Resistance Nanosheet Cell Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of multi-gate transistors to the 10 nanometer node or sub-10 nanometer range, leading to challenges in optimizing device performance and efficiency.
Innovation Solution
Implementing deep via bar width tuning in integrated circuit structures, which allows for self-aligned fabrication and recessed via bars, optimizing resistance and capacitance trade-offs, and enabling power delivery from the backside, thereby reducing cell height and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing manufacturing infrastructure can be maintained, but manufacturing precision deteriorates at 10 nanometer node or sub-10 nanometer range
Solution Approach 1:
The patent changes the geometric parameters of the via bar structure by introducing width tuning (different widths at different depths) and recessed configurations. This allows optimization of the via bar dimensions to compensate for fabrication process variability, achieving better manufacturing precision at 10nm and sub-10nm nodes by adjusting the via bar width profile rather than relying solely on conventional fixed-dimension via structures
Solution Approach 2:
The patent transitions from conventional planar via structures to three-dimensional via bar structures with varying widths through different depths. By introducing the depth dimension with width tuning (wider at certain depths, narrower at others) and recessed configurations, the design achieves better control over electrical properties and mechanical stability, resolving the precision-reliability contradiction through dimensional enhancement
2Loss of energy
If via bar width is increased to reduce resistance, then power network resistance decreases, but cell height increases
Solution Approach 1:
The patent applies local quality by implementing width tuning where the via bar has different widths at different depths rather than a uniform width. The via bar is wider at certain depths (where resistance reduction is most beneficial) and narrower at other depths, allowing localized optimization of resistance without uniformly increasing the via bar footprint and cell height
Solution Approach 2:
The patent resolves the resistance-height contradiction by moving from a two-dimensional via cross-section to a three-dimensional via bar structure with varying width through depth. This dimensional transformation allows the via bar to achieve lower resistance through optimized volume distribution while maintaining a compact overall height by utilizing the depth dimension for width modulation
3Speed
If via bar to gate-end distance is reduced to improve performance, then transistor switching speed increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-positioning the via bar in a recessed configuration and pre-defining its width profile before final interconnect formation. The via bar is prepared in advance with optimized dimensions and positioning, allowing subsequent processing steps to proceed with standard precision requirements while achieving the performance benefits of reduced via bar to gate-end distance
Solution Approach 2:
The patent provides beforehand cushioning by designing the via bar with a recessed configuration and width tuning that creates a buffer zone. The recessed via bar provides mechanical and electrical cushioning that compensates for positioning variations, allowing reduced via bar to gate-end distance without proportionally increasing manufacturing precision requirements through built-in tolerance compensation
Data Source
AI summary
Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.