Deep Via Dielectric Liner for Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
As transistor cell density increases in integrated circuits, it becomes challenging to scale the lowest interconnect metallization levels while maintaining low external resistance and parasitic capacitance, particularly due to the proximity of metallization to transistor terminals, which leads to increased capacitance.
Innovation Solution
The implementation of a deep via with a dielectric liner that extends from one side of a transistor semiconductor body to the other, electrically insulated from at least one transistor terminal, and includes a dielectric liner on its sidewall to reduce parasitic capacitance by increasing lateral separation between metallization and transistor terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If self-alignment techniques are used to place metallization in close proximity to transistor terminals, then transistor cell density increases, but parasitic capacitance increases
Solution Approach 1:
The patent introduces a vertical dimension solution by forming deep vias that extend through the transistor cell structure. Instead of only lateral spacing, the via extends vertically to provide capacitance reduction while maintaining horizontal proximity for high density. The dielectric liner on the via sidewall provides the capacitance reduction mechanism in this vertical configuration.
Solution Approach 2:
The dielectric liner material acts as an intermediary between the via fill material and the transistor terminals. This intermediate layer provides electrical isolation and reduces parasitic capacitance coupling between the conductive via and adjacent transistor terminals, while still allowing the via to serve its interconnect function.
2Object-generated harmful factors
If lateral spacing between metallization and transistor terminals is increased to reduce capacitance, then parasitic capacitance decreases, but transistor cell footprint increases
Solution Approach 1:
The solution moves from lateral spacing to vertical extension. The deep via extends in the vertical dimension (z-dimension) rather than requiring increased horizontal spacing. This allows the via to achieve sufficient capacitance reduction through vertical dielectric separation while maintaining compact horizontal footprint for high-density cell layout.
3Area of stationary object
If deep via metallization is placed close to transistor terminals for compact layout, then transistor cell footprint decreases, but parasitic capacitance increases
Solution Approach 1:
The dielectric liner serves as a mediating layer between the via metallization and transistor terminals. Even when the via is positioned close to terminals for compact footprint, the dielectric liner provides the necessary electrical isolation and capacitance reduction, enabling close placement without the harmful capacitance effect.
Solution Approach 2:
The dielectric liner forms a thin film structure on the via sidewall that provides effective capacitance reduction. This thin dielectric layer is sufficient to reduce parasitic capacitance while occupying minimal space, allowing the via to be positioned close to terminals without increasing cell footprint.
Data Source
AI summary
A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.