Deep Via Construction Lateral Contact for Thermal Stress Relief
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Solution Overview
Problem
Deep vias in integrated circuit semiconductor devices, especially those filled with metals like copper, experience thermal expansion issues, leading to stress and potential cracks or delamination in surrounding dielectric and metal layers during thermal processing, particularly in three-dimensional chip stacking applications.
Innovation Solution
The contact area for the metal fill is relocated laterally within the deep via, avoiding contact with the upper surface of the metal fill, and a metal barrier layer is used to connect the metal fill to interconnect wiring, with a recessed upper surface of the metal fill and an anti-adhesion coating to minimize stress and prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact area is located above the upper surface of the metal fill, then electrical connection is achieved, but thermal expansion causes stress and cracks in surrounding layers
Solution Approach 1:
The contact area is moved from a vertical position (above the metal fill) to a lateral position (at the same level as the metal fill sidewall). This dimensional relocation allows the contact area to remain electrically connected to the metal fill while being positioned outside the thermal expansion zone, thereby eliminating stress on overlying dielectric layers.
Solution Approach 2:
The via structure is segmented into distinct functional zones: the metal fill for electrical conduction, the lateral contact area for electrical connection, and the recessed upper surface for stress relief. This segmentation allows each component to perform its function independently without interfering with others, particularly isolating the dielectric layers from thermal expansion forces.
2Reliability
If deep vias are filled with copper, then electrical conductivity is improved, but thermal expansion causes delamination of dielectric layers
Solution Approach 1:
The lateral contact area acts as an intermediary element between the metal fill and the interconnect wiring. It provides the electrical connection function while being positioned laterally to avoid transmitting thermal expansion forces to the dielectric layers, thus mediating between electrical conductivity requirements and structural stability.
Solution Approach 2:
The position parameter of the contact area is changed from vertical (above metal fill) to lateral (at metal fill sidewall level). This parameter change fundamentally alters the stress transmission characteristics, allowing copper fills to maintain high conductivity while the lateral positioning prevents stress transmission to dielectric layers during thermal cycling.
3Reliability
If the metal fill expands thermally, then electrical conductivity is maintained, but surrounding dielectric layers experience severe stress
Solution Approach 1:
The contact function is extracted from the vertical stack and placed laterally at the metal fill sidewall. This extraction removes the source of stress transmission to dielectric layers while preserving the electrical connection function, allowing the metal fill to expand freely without affecting surrounding layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces thermal stress on the surrounding layers, preventing cracks and delamination by allowing the metal fill to expand without exerting pressure on the dielectric layers, ensuring reliable electrical connections and maintaining structural integrity during thermal processing.
Implementation Method 1
Copper, for example, has a coefficient of thermal expansion (CTE) of around 16 ppm/° C. This means that a typical 50 μm deep copper filled via will expand in length by approximately 300 nm when it is heated from room temperature to 400° C
Data Source
AI summary
An integrated circuit semiconductor device includes a substrate, a deep via within the substrate which is provided with a dielectric cladding in contact with the substrate, metal fill located within the deep via and defining an upper surface, interconnect wiring, and a dielectric layer located above the deep via and a void between the upper surface of the metal fill and the dielectric layer. The interconnect wiring layer contacts the metal fill laterally.