Deep Via Interconnects for Minimum-Area Routing Constraints
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Solution Overview
Problem
Integrated circuits face congestion issues due to an increased number of pins for routing input signals, which violates metallization minimum area rules and leads to inefficiencies in semiconductor device design and manufacturing.
Innovation Solution
The use of deep via structures to connect metallization layers alleviates congestion by reducing the area required for input pins and local routing, allowing for compliance with design rules without violating minimum area constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of pins for routing input signals is increased, then the routing capability is improved, but the metallization layer congestion increases and minimum area rules are violated
Solution Approach 1:
The patent introduces deep via structures that extend vertically through multiple metallization layers, transitioning the routing problem from a two-dimensional planar constraint to a three-dimensional solution. By utilizing the vertical dimension with deep vias connecting different metallization layers (e.g., M1, M2, M3), the design achieves improved routing capability without increasing the horizontal area occupied in any single metallization layer, thus avoiding congestion and minimum area rule violations.
2Area of stationary object
If deep via structures are used to connect metallization layers, then the congestion in metallization layers is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the via structures into different types: shallow vias connecting adjacent metallization layers and deep vias spanning multiple layers. This segmentation allows the manufacturing process to handle each via type with appropriate process parameters, reducing overall complexity. The shallow vias can be formed with standard via processes, while deep vias use specialized but isolated process steps, making the combined approach more manageable than a single complex via type.
Solution Approach 2:
The patent utilizes parameter changes in the via formation process, specifically adjusting etch depth and fill parameters to create different via types (shallow vs. deep) within the same metallization structure. By controlling the etch depth parameter, the process can selectively form shallow vias for local connections and deep vias for long-distance routing, enabling flexible area management without requiring entirely different manufacturing approaches.
3Manufacturing precision
If the area for input pins and local routing is reduced, then the design rule compliance is improved, but the routing efficiency may be compromised
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through deep via structures that connect distant points across multiple metallization layers. This allows short horizontal trace lengths in each layer (maintaining design rule compliance) while achieving long-distance electrical connections (maintaining routing efficiency). The deep vias act as vertical shortcuts that eliminate the need for long meandering routes in the planar direction.
Solution Approach 2:
The deep via structures serve as intermediary elements that bridge distant regions of the circuit across multiple metallization layers. Rather than requiring long horizontal conductors that would violate minimum area rules, the deep vias provide a vertical mediation path that maintains both design rule compliance and routing efficiency by connecting input pins and local routing to distant destinations through the third dimension.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.