Deep Via Metallization Layout for Routing Congestion Relief
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Solution Overview
Problem
The increasing number of pins for routing input signals leads to wiring/metallization congestion in semiconductor devices, violating minimum area rules and complicating routing processes.
Innovation Solution
The use of deep via structures to connect metallization layers alleviates congestion by reducing the area required in metallization layers, thereby avoiding violations of minimum area rules and simplifying routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of pins for routing input signals is increased, then the routing capability is improved, but wiring/metallization congestion occurs and minimum area rules are violated
Solution Approach 1:
The patent introduces deep via structures that extend vertically through multiple metallization layers, transitioning from a two-dimensional routing approach to a three-dimensional one. This allows input signals to be routed through the vertical dimension (deep vias spanning from lower to upper metallization layers), thereby reducing congestion in individual metallization layers while maintaining enhanced routing capability.
2Ease of operation
If deep via structures are used to connect metallization layers, then congestion in metallization layers is reduced, but manufacturing complexity increases
Solution Approach 1:
The deep via structures are segmented into multiple portions spanning different metallization layers (lower metallization layer, intermediate metallization layers, upper metallization layer). Each segment can be formed and filled independently through separate via formation processes, allowing the complex vertical interconnection to be broken down into manageable manufacturing steps.
Data Source
AI summary
A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.