Deep Via Interconnects for Scalable Stacked CMOS Transistors
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Solution Overview
Problem
There is a continued desire for further scaling and reducing the size of field-effect transistors (FETs) beyond conventional techniques such as FinFETs and stacked nanosheet channels, particularly for next-generation stacked FET devices.
Innovation Solution
The development of deep via structures for stacked transistor devices, which connect frontside and backside interconnect wiring levels through vias and local interconnect layers, allowing for efficient signal and power transmission between stacked complementary metal-oxide-semiconductor (CMOS) architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET scaling techniques (FinFETs, stacked nanosheet channels) are used, then transistor size is reduced, but further scaling beyond these techniques becomes difficult
Solution Approach 1:
The patent transitions from planar 2D scaling to 3D vertical stacking by implementing multiple device layers stacked vertically with deep vias connecting interconnect wiring levels between layers. This dimensional change enables continued scaling beyond the limits of conventional FinFET and nanosheet channel techniques by utilizing the vertical dimension for additional device layers and interconnect levels.
2Area of stationary object
If stacked transistor architectures are implemented, then device area footprint is reduced, but electrical connections between stacked layers become more complex
Solution Approach 1:
The patent segments the interconnect structure into local interconnect layers and deep vias, where local interconnect layers provide lateral connections within each device layer and deep vias provide vertical connections between layers. This segmentation simplifies the overall connection complexity by breaking down the challenging through-silicon via requirements into more manageable local interconnect segments that can be formed using standard semiconductor fabrication techniques.
Solution Approach 2:
The patent introduces local interconnect layers as intermediary structures between stacked device layers. These local interconnect layers act as mediator elements that facilitate electrical connections between deep vias and contact regions, enabling efficient signal and power transmission between layers without requiring direct through-silicon via connections, thereby reducing fabrication complexity.
3Reliability
If deep vias are used to connect interconnect wiring levels, then electrical connections between stacked layers are enabled, but via formation and filling become more difficult
Solution Approach 1:
The patent divides the vertical interconnect path into segments: deep vias for vertical access and local interconnect layers for lateral connections. This segmentation allows each component to be optimized independently - deep vias can be formed to appropriate depths and filled with conductive material, while local interconnect layers provide the remaining connection functionality, making the overall manufacturing process more achievable with current fabrication capabilities.
Solution Approach 2:
The patent resolves via formation difficulties by transitioning from requiring single deep through-silicon vias to using combinations of shallower deep vias connected to local interconnect layers. This dimensional approach distributes the via depth requirement across multiple levels, making each via formation step more manageable while achieving the same overall electrical connection functionality between stacked layers.
Data Source
AI summary
A semiconductor device comprises a plurality of first transistors, a plurality of second transistors stacked on the plurality of first transistors, and a first dielectric layer and a second dielectric layer between the plurality of first transistors and the plurality of second transistors. The second dielectric layer is stacked on the first dielectric layer. The semiconductor device also comprises an interconnect layer between the first dielectric layer and the second dielectric layer, a first interconnect wiring level on a first side of a stacked structure comprising the plurality of second transistors stacked on the plurality of first transistors, and a second interconnect wiring level on a second side of the stacked structure opposite the first side. A via is electrically connected to and disposed between the first and second interconnect wiring levels, wherein the via is further electrically connected to the interconnect layer.