Deep Vision Processor With Banked Registers for Low-Power AI
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Solution Overview
Problem
The high computation cost and power consumption of neural network and deep learning algorithms in embedded devices pose a barrier to their widespread adoption, particularly in battery-operated devices and those requiring thermal management, while specialized chips lack flexibility and programmability.
Innovation Solution
A programmable deep vision processor architecture with a load and store unit, banked register file, and arithmetic logic units that efficiently handle image pixel and stencil data, enabling concurrent operations and reducing power consumption and cost compared to GPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If programmable general purpose GPUs are used for deep learning computations, then flexibility and programmability are improved, but power consumption increases significantly
Solution Approach 1:
The processor is segmented into multiple specialized functional units including a load and store unit for data movement, a register unit with banked register file for high-speed storage, an interconnect unit for data routing, and multiple arithmetic logic units for parallel computations. This segmentation allows each unit to be optimized for its specific function, achieving high programmability while reducing overall power consumption compared to a general-purpose GPU.
2Use of energy by moving object
If specialized fixed function accelerators are used for deep learning, then power consumption is reduced, but flexibility and programmability are lost
Solution Approach 1:
The processor implements a universal architecture that can perform multiple deep learning operations including convolutions, activations, and pooling through its arithmetic logic units. The banked register file and interconnect unit provide a flexible data path that can be configured for different neural network layers and operations, enabling the processor to adapt to various deep learning algorithms while maintaining low power consumption through specialized hardware design.
3Productivity
If high computation power is provided for deep learning algorithms, then processing speed is improved, but cost and power consumption increase
Solution Approach 1:
The processor utilizes 8-bit integer arithmetic in its arithmetic logic units, changing the parameter of numerical precision from traditional 32-bit or 64-bit floating point to 8-bit integers. This parameter change enables higher computation speeds with lower power consumption, as 8-bit operations require fewer transistors and less energy while still providing sufficient precision for many deep learning applications. The banked register file further enhances this by providing high-speed data access that keeps the computation units fully utilized.
Data Source
AI summary
Disclosed herein is a processor for deep learning. In one embodiment, the processor comprises: a load and store unit configured to load and store image pixel data and stencil data; a register unit, implementing a banked register file, configured to: load and store a subset of the image pixel data from the load and store unit, and concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry; and a plurality of arithmetic logic units configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and corresponding stencil data of the stencil data.