Deeply Depleted Channel Transistors for Digital Circuit Power Reduction
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Solution Overview
Problem
Conventional digital circuits face challenges in reducing power consumption, improving performance, and minimizing size due to limitations in scaling, which are costly and technically challenging as device fabrication approaches its limits.
Innovation Solution
The use of 'deeply depleted channel' (DDC) transistors with a highly doped screening layer and an undoped channel region, allowing for body biasing to adjust threshold voltage, is employed in digital circuits to enhance performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional transistors are used in digital circuits, then manufacturing is easier, but power consumption is higher and performance is limited
Solution Approach 1:
The patent applies local quality by creating distinct regions within the transistor structure: a highly doped screening layer region and an undoped channel region. This localized differentiation of doping concentrations allows the transistor to achieve lower power consumption through reduced threshold voltage while maintaining manufacturability through controlled local doping processes rather than complete restructuring of the device.
Solution Approach 2:
The patent changes the doping parameter from uniform (conventional) to non-uniform (highly doped screening layer with undoped channel). This parameter change in the doping concentration profile enables the transistor to operate at lower power consumption by reducing threshold voltage, while the changes are achieved through standard semiconductor processing techniques that maintain ease of manufacture.
2Productivity
If device size is reduced to improve circuit density, then more devices fit on substrate, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses local quality with highly doped screening layers confined to specific regions beneath the channel. This localized doping approach allows for precise control of electrical properties in small devices without requiring ultra-precise manufacturing across the entire structure. The undoped channel region maintains simplicity while the localized doped regions provide the necessary electrical control for high-density circuits.
3Reliability
If threshold voltage variations are minimized to improve circuit stability, then signal distribution improves, but device complexity increases
Solution Approach 1:
The patent achieves improved circuit stability through local quality by placing highly doped screening layers in specific regions beneath the channel. This localized approach reduces threshold voltage variations and improves signal distribution without requiring complex device structures. The simplicity of the undoped channel combined with localized doped regions provides stability while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in faster signal propagation, reduced power consumption, and smaller circuit sizes, leading to improved performance and cost savings by minimizing variations in threshold voltage and signal distribution.
Implementation Method 1
deeply depleted channel (DDC) transistors with a highly doped screening layer and an undoped channel region, allowing for body biasing to adjust threshold voltage
Data Source
AI summary
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.