Multiple Defect Diagnosis via Seed Net Tree Similarity
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Solution Overview
Problem
Current multiple defect diagnosis methods in IC manufacturing are time-consuming and expensive, particularly when dealing with multiple defects, as they require extensive iterative simulations and testing, which is inefficient and costly.
Innovation Solution
A method that involves receiving a gate-level netlist and test patterns, deriving seed nets, calculating similarities between them to generate a single seed-net tree, and identifying suspected seed nets to reduce the need for iterative simulations and testing by analyzing correlations between erroneous outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative multiple fault simulation is used to find faults one at a time, then diagnostic accuracy is improved, but time consumption and computational cost increase significantly
Solution Approach 1:
The patent segments the diagnostic process into two phases: (1) generating multiple candidate faults in parallel from test failures, and (2) iteratively selecting and verifying faults. This segmentation allows the system to generate comprehensive fault candidates simultaneously rather than sequentially, reducing time consumption while maintaining diagnostic accuracy through subsequent verification steps.
Solution Approach 2:
The patent performs preliminary action by generating all candidate faults in advance using test failures and simulation before the actual diagnostic selection process. By pre-computing the fault candidate set and their coverage of test failures, the system avoids time-consuming iterative simulations during the diagnostic phase, significantly reducing overall time consumption while preserving accuracy.
2Measurement precision
If multiple iterations of testing with diagnostic patterns are performed, then fault distinction capability is improved, but production cost increases
Solution Approach 1:
The patent uses fault simulation to create virtual copies of test failures and generates simulated failure patterns for candidate faults. By working with these simulated copies rather than performing multiple physical testing iterations, the system achieves fault distinction capability at lower production cost, avoiding the expenses associated with repeated ATE testing.
Solution Approach 2:
The patent changes the parameter of test application by using simulated test patterns derived from fault simulation rather than physical test patterns. This parameter change allows the system to evaluate fault distinction capability through computational analysis of simulated responses, significantly reducing production costs compared to multiple physical testing iterations while maintaining diagnostic effectiveness.
3Reliability
If comprehensive fault simulation is performed to cover all test failures, then diagnostic completeness is improved, but computational complexity increases
Solution Approach 1:
The patent applies partial action by generating candidate faults that may exceed the minimum needed to cover test failures, then using selection criteria to identify the most relevant faults. This approach ensures diagnostic completeness by considering a comprehensive set of candidates while managing computational complexity through efficient selection and verification processes that focus computational resources on the most promising candidates.
Data Source
AI summary
A multiple defect diagnosis method includes: receiving a gate-level netlist of a chip, a plurality of test patterns and a plurality of test failure reports; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test patterns and the plurality of test failure reports; utilizing a processor to compute similarity between the plurality of seed nets, and accordingly merging the plurality of seed nets to obtain a single seed net tree; and deriving at least one suspected seed net according to the single seed net tree.