Defect Trapping Layers for Strained Channel Semiconductor Devices
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Solution Overview
Problem
The co-integration of n-MOS and p-MOS devices on a common substrate is challenging due to differences in material requirements and strain conditions, leading to difficulties in forming high-performance devices with low defect densities, as thick buffer layers cause substrate bowing and defect propagation, while thin layers may allow defects to migrate into channel regions, reducing charge carrier mobility.
Innovation Solution
The use of a relaxed SiGe layer with a defect trapping mechanism, such as patterned dielectric layers or superlattice structures, to prevent defect migration into strained channel regions, allowing for the co-integration of tensile-strained n-MOS and compressive-strained p-MOS devices on the same substrate with reduced defect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick buffer layer is used to prevent defect migration into channel regions, then defect blocking is improved, but substrate bowing increases and manufacturing complexity worsens
Solution Approach 1:
The buffer layer is segmented into multiple thinner layers with alternating materials (e.g., SiGe and Si) creating a superlattice structure. This segmentation prevents substrate bowing while maintaining defect blocking capability, as each thin layer relaxes strain independently without causing cumulative substrate deformation.
Solution Approach 2:
The buffer layer uses composite materials with alternating compositions (e.g., SiGe/Si superlattice) to achieve both defect blocking and substrate flatness. The composite structure provides strain management while preventing defect migration into channel regions.
2Device complexity
If a thin buffer layer is used to reduce substrate bowing, then manufacturing is simplified, but defect migration into channel regions increases
Solution Approach 1:
The thin buffer layer uses composite materials (SiGe/Si superlattice) to compensate for the reduced thickness. The alternating material structure provides strain management and defect blocking functionality that would otherwise require a much thicker single-layer buffer.
Solution Approach 2:
The buffer layer parameters are changed from a single thick layer to multiple thin layers with varying compositions. This parameter change maintains defect blocking efficiency while reducing overall substrate stress and bowing.
3Speed
If strained channel regions are formed to improve charge carrier mobility, then device performance is enhanced, but defect density increases
Solution Approach 1:
The relaxed SiGe buffer layer acts as an intermediary between the substrate and the strained channel region. It provides the necessary strain to enhance charge carrier mobility while preventing defect migration from the substrate into the channel, thus maintaining low defect density.
4Adaptability or versatility
If co-integration of n-MOS and p-MOS devices is implemented on a common substrate, then device versatility is improved, but material compatibility challenges increase
Solution Approach 1:
The buffer layer structure is optimized with local quality variations to accommodate both n-MOS and p-MOS devices. Different regions of the buffer layer can be tailored with appropriate SiGe compositions to provide the specific strain conditions required for each device type while maintaining overall structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of low defect density semiconductor devices with enhanced charge carrier mobility by trapping defects and maintaining strain-induced performance improvements, avoiding substrate bowing and defect propagation issues.
Implementation Method 1
a defect trapping layer (or layers) prevent defects from migrating into channel regions of the co-integrated n-MOS and p-MOS devices
Implementation Method 2
The superlattice structure may include, for instance, alternating layers of semiconductor material and dielectric material
Data Source
AI summary
Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.