Defective P-N Junction for FDSOI Backbias Stability

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Solution Overview

Problem

In backgated fully depleted silicon on insulator (FDSOI) MOSFETs, the p-n junction's leakage resistance is inadequate during AC operation due to capacitive voltage dividers, causing fluctuations in the applied backbias voltage.

Innovation Solution

Creating defects at the p-n junction interface between the well and the pocket, either as part of the same implantation used to form the pocket or through a separate blanket implantation, to intentionally reduce the leakage resistance and ensure most of the applied voltage drops at the buried oxide interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a p-n junction is formed between the well and pocket to apply backbias, then the backbias can be applied to the BOX, but during AC operation a capacitive voltage divider is formed causing the actual backbias to fluctuate

Engineering Contradiction:
Improvebackbias applicationVSAvoidbackbias stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent intentionally creates defects at the p-n junction to increase leakage current, converting the harmful effect of leakage into a beneficial effect. The increased leakage provides a low-impedance path that stabilizes the backbias voltage during AC operation by preventing the capacitive voltage divider from causing fluctuations, thus converting the previously harmful leakage into a stabilizing mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the electrical parameters of the p-n junction by introducing defects that increase leakage current. This parameter change transforms the p-n junction from a high-impedance capacitive element into a low-impedance conductive path, fundamentally altering its behavior in the AC regime and eliminating the voltage divider effect.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If the p-n junction has high leakage resistance, then DC operation is maintained, but during AC operation the capacitive voltage divider causes voltage fluctuations

Engineering Contradiction:
ImproveDC operation stabilityVSAvoidAC operation performance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent makes the p-n junction's electrical characteristics dynamic by frequency-dependent behavior. The introduced defects create a leakage path that is particularly effective at AC frequencies, allowing the junction to maintain its capacitive characteristics at DC while providing a low-impedance path during AC operation, thus adapting its behavior to different operating conditions.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach makes the p-n junction leaky, allowing most of the AC signal to drop across the buried oxide, effectively addressing the voltage divider issue and stabilizing the backbias voltage during AC operation.

Implementation Method 1

during AC operation, there is a capacitive voltage divider formed by the MOS (metal-oxide-semiconductor) capacitor associated with the BOX and the depletion capacitor associated with the p-n junction between the well and pocket

Methodology Applied
Scientific EffectCapacitive voltage divider: Capacitance

Implementation Method 2

Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased

Methodology Applied
Scientific EffectLeakage current reduction through defect creation: Electrical Resistance

Data Source

PatentUS9373507B2Defective P-N junction for backgated fully depleted silicon on insulator mosfet
Publication Date: 2016.06.21 STMICROELECTRONICS INC
  • US9373507B2 patent drawing
  • US9373507B2 patent drawing
  • US9373507B2 patent drawing

AI summary

Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.