Defer Buffer for In-Order Processor Inter-Thread Blocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In-order processors face inter-thread blocking issues where a stalled instruction prevents progress in other threads, leading to reduced performance due to limited resource utilization and commit circuitry restrictions.
Innovation Solution
The implementation of a defer buffer to store blocked instructions that have completed execution but are not yet committed due to earlier incomplete instructions, allowing other threads to progress by moving these instructions out of functional units and enabling their commitment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If instructions are committed in program order for each thread, then correctness is maintained, but inter-thread blocking occurs when an earlier instruction is incomplete
Solution Approach 1:
The patent segments the instruction commit process by introducing a defer buffer that separates instructions into two categories: those ready for immediate commit and those that must be deferred. This segmentation allows the commit circuitry to commit instructions from different threads independently, breaking the blocking chain while maintaining program order within each thread.
Solution Approach 2:
The defer buffer acts as an intermediary structure between the execution units and the commit circuitry. It temporarily holds instructions that have completed execution but cannot yet be committed due to program order constraints, allowing other threads' instructions to proceed through the commit stage without blocking.
2Stability of the object's composition
If a stalled instruction is held in the functional unit, then execution dependencies are maintained, but resource utilization decreases
Solution Approach 1:
The patent extracts stalled instructions from the functional units and places them in the defer buffer. This extraction removes the blocking effect on other threads' instructions while preserving the execution order constraints for the stalled thread, as the defer buffer maintains the necessary ordering information.
Solution Approach 2:
The patent adds a temporal dimension to instruction handling by introducing the defer buffer as an intermediate storage stage. Instructions are moved from the execution dimension (functional units) to the buffering dimension (defer buffer), allowing parallel progression of other threads while the stalled instruction waits for its dependency to resolve.
3Productivity
If multiple threads share the same pipeline resources, then resource utilization improves, but inter-thread blocking increases
Solution Approach 1:
The defer buffer implementation allows each thread to manage its own instruction flow independently. The commit circuitry checks program order constraints specific to each thread and only defers instructions when necessary, allowing other threads to proceed without interference. This self-service approach minimizes inter-thread blocking while maintaining simple per-thread management logic.
Data Source
AI summary
An apparatus comprises processing circuitry for executing instructions of two or more threads of processing, hardware registers to store context data for the two or more threads concurrently, and commit circuitry to commit results of executed instructions of the threads, where for each thread the commit circuitry commits the instructions of that thread in program order. At least one defer buffer is provided to buffer at least one blocked instruction for which execution by the processing circuitry is complete but execution of an earlier instruction of the same thread in the program order is incomplete. This can help to resolve inter-thread blocking and hence improve performance.