Deferred ECC Scheduling for DRAM Bandwidth Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic random-access memory (DRAM) systems employing inline error correction codes (ECC) face a bandwidth penalty due to the use of ECC parity bits as payload, which consumes data bandwidth between DRAM and the system-on-a-chip (SoC), affecting overall system performance.
Innovation Solution
The solution involves deferring ECC operations during memory read and write operations based on pre-configured triggers, such as high bus utilization or explicit commands, allowing exclusive bus utilization for user data and performing deferred ECC processing when conditions are met, thereby improving bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC parity bits are transmitted as payload during memory operations, then error detection and correction capability is maintained, but data bandwidth between DRAM and SoC is reduced
Solution Approach 1:
The patent applies preliminary action by pre-configuring triggers that determine when ECC operations should be deferred. The system prepares and stores ECC parity bits in advance during deferred periods, then applies them when triggers indicate appropriate timing, thereby separating ECC processing from the critical data path and improving bandwidth without sacrificing error correction capability
Solution Approach 2:
The patent segments the ECC operation into distinct phases: deferred ECC generation/storage and subsequent ECC application. By dividing the ECC process into separable stages that can occur at different times, the system allows data operations to proceed without being blocked by ECC processing, thus improving bandwidth while maintaining reliability
2Reliability
If ECC operations are performed inline during memory reads and writes, then data integrity is ensured, but bus utilization is reduced due to shared bandwidth
Solution Approach 1:
The patent implements periodic action by using pre-configured triggers to determine when ECC operations should be deferred versus performed inline. The system alternates between deferred ECC processing during high-utilization periods and inline ECC operations during lower-utilization periods, optimizing the balance between data integrity and bus utilization dynamically
Solution Approach 2:
The patent extracts the ECC operation from the critical data path by deferring it to separate processing periods. ECC parity bits are generated and stored separately during deferred periods, then applied to data when triggers indicate appropriate timing, removing the bottleneck from the main data transmission path and improving bus utilization
Data Source
AI summary
A deferred error correction code (ECC) scheme for memory devices is disclosed. A disclosed method includes starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.