Deferred ECC Scheduling for Higher Memory Bus Bandwidth
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Solution Overview
Problem
The existing DRAM systems employing inline error correction codes (ECC) suffer from bandwidth penalties due to the allocation of data bandwidth for ECC parity bits, which reduces overall system performance.
Innovation Solution
The proposed solution involves deferring ECC operations during memory read and write operations based on pre-configured triggers, such as high bus utilization or explicit commands, allowing exclusive bus utilization for user data and performing deferred ECC processing when conditions are met, thereby improving bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC parity bits are transmitted as payload during reads/writes, then data integrity is ensured, but effective data bandwidth is reduced
Solution Approach 1:
The patent applies preliminary action by pre-configuring triggers that determine when ECC operations should be deferred. The system proactively identifies conditions (such as high bus utilization or explicit commands) before they become problematic, and prepares to defer ECC operations in advance. This allows the system to maintain data integrity while optimizing bandwidth usage by deferring ECC processing to appropriate moments rather than always performing it synchronously with data transfers.
Solution Approach 2:
The patent implements dynamics by making the ECC operation timing flexible and adaptive rather than fixed. The system dynamically adjusts whether to perform ECC operations inline or defer them based on real-time conditions monitored by pre-configured triggers. This dynamic approach allows the system to switch between different operational modes (inline ECC vs. deferred ECC) to optimize the trade-off between data integrity verification and effective bandwidth utilization based on current system state.
2Reliability
If ECC operations are performed inline during reads/writes, then data errors are detected and corrected immediately, but bus utilization is reduced due to ECC data transmission
Solution Approach 1:
The patent applies the extraction principle by separating ECC operations from the main data transfer path. Instead of always performing ECC operations inline during data reads/writes, the system extracts ECC processing into a deferred operation that can be performed separately when triggers indicate appropriate conditions. This extraction allows bus resources to be dedicated exclusively to user data during critical transfer periods, improving overall bus utilization while maintaining error detection and correction capabilities through deferred ECC processing.
3Productivity
If deferred ECC operations are implemented, then bus resources are dedicated to user data, but ECC processing is delayed
Solution Approach 1:
The patent implements feedback by using pre-configured triggers that monitor system conditions and determine when deferred ECC operations should be executed. The triggers provide feedback mechanisms that watch for appropriate conditions (such as reduced bus utilization or specific system states) and activate ECC processing when those conditions are met. This feedback-driven approach ensures that ECC operations are deferred only when appropriate and executed promptly when conditions permit, minimizing processing delays while maintaining high bus resource utilization for user data transfers.
Data Source
AI summary
A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.