Deferred Inter-Processor Interrupts for Power and Latency Trade-offs

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Solution Overview

Problem

In multi-processor systems, existing strategies for handling interrupts lead to scheduling latency and power inefficiency due to unnecessary wake-ups of processors, as they either delay runnable threads or wake up multiple processors for minimal workloads.

Innovation Solution

Implementing a deferred inter-processor interrupt (IPI) mechanism, where a first processor issues a deferred IPI that can be cancelled if it completes processing before a timer expires, allowing the first processor to handle new interrupts without waking up a second processor unless necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the first processor chooses not to wake up the second processor, then power consumption is reduced, but scheduling latency increases for the newly runnable thread

Engineering Contradiction:
Improvepower consumptionVSAvoidscheduling latency
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The system dynamically adjusts processor wake-up behavior based on real-time conditions. The deferred IPI mechanism allows the system to postpone the decision to wake up the second processor, and the ability to cancel the deferred IPI enables dynamic adaptation if the first processor becomes available sooner than expected. This dynamic approach resolves the contradiction by making the wake-up decision flexible rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary action by issuing a deferred IPI that can be cancelled. This preliminary wake-up request is prepared in advance but remains cancellable, allowing the system to avoid actual wake-up if unnecessary. This resolves the contradiction by having a pre-prepared solution that can be activated or cancelled based on runtime conditions.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the operating system chooses to wake up the second processor as soon as the thread is made runnable, then scheduling latency is minimized, but power efficiency deteriorates due to unnecessary wake-ups

Engineering Contradiction:
Improvescheduling latencyVSAvoidpower efficiency
Core Design Contradiction:
Loss of timeVSLoss of energy

Solution Approach 1:

The system uses feedback by monitoring whether the first processor completes its current interrupt processing before the deferred IPI timeout. This feedback mechanism allows the system to determine whether the second processor needs to be woken up, resolving the contradiction by making the wake-up decision based on actual system state rather than assumption.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes the parameter of IPI timing from immediate to deferred with a timeout value. This parameter change allows the system to delay the wake-up decision and potentially cancel it, resolving the contradiction between minimizing latency and maximizing power efficiency by adjusting the timing parameter based on system needs.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If the first processor handles the new interrupt immediately, then scheduling latency is reduced, but the ability to save power deteriorates due to potential unnecessary processor wake-ups

Engineering Contradiction:
Improvescheduling latencyVSAvoidpower savings
Core Design Contradiction:
Loss of timeVSLoss of energy

Solution Approach 1:

The system dynamically chooses between handling the interrupt immediately on the first processor or waking up the second processor based on whether the deferred IPI times out. This dynamic decision-making resolves the contradiction by allowing the system to optimize for power savings when possible while still providing a path for low-latency handling when necessary.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10649935B2Deferred inter-processor interrupts
Publication Date: 2020.05.12 APPLE INC
  • US10649935B2 patent drawing
  • US10649935B2 patent drawing
  • US10649935B2 patent drawing

AI summary

A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.