Deferred Interrupt Mechanism for Shared Memory Polling
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Solution Overview
Problem
In inter-process and inter-partition communication schemes, the continuous polling of shared memory locations for messages can lead to severe performance issues, especially in moderately to highly loaded systems, due to the high cost of sending and servicing interrupts, which can impact system performance.
Innovation Solution
A method is introduced where a message is written to a shared memory location with a request for an interrupt to be sent after a specified latency has elapsed, using a trigger memory to store pending interrupts, allowing for deferred interrupt handling and reducing unnecessary polling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous polling is used to check shared memory for messages, then messages can be detected promptly, but processor performance deteriorates due to continuous utilization of CPU cycles
Solution Approach 1:
The system transitions from continuous polling to periodic interrupt-driven action. The receiver process is interrupted only when messages are available in shared memory, converting continuous CPU utilization into periodic, event-driven processing. This resolves the contradiction by maintaining message detection reliability while eliminating wasteful continuous polling that degrades processor performance.
Solution Approach 2:
The shared memory location serves itself by automatically generating interrupt signals when message counts change. Instead of requiring the receiver to continuously check for messages, the system self-notifies the receiver through hardware-generated interrupts, freeing the processor from active polling while ensuring timely message detection.
2Speed
If interrupts are sent immediately when messages are written to shared memory, then message processing is prompt, but system performance deteriorates in moderately to highly loaded systems due to the high cost of sending and servicing interrupts
Solution Approach 1:
The system performs preliminary batching of interrupt generation. Instead of sending an interrupt for every single message written to shared memory, the system accumulates multiple messages and generates a single interrupt when a threshold is reached or after a timeout period. This preliminary action reduces the frequency of expensive interrupt operations while maintaining acceptable message processing speed through batched handling.
Solution Approach 2:
The interrupt generation mechanism is made dynamic by adjusting interrupt thresholds and timeout values based on system load conditions. In high-load scenarios, the system increases the number of messages required to trigger an interrupt, reducing interrupt frequency. In low-load scenarios, it decreases the threshold for faster response. This dynamic adaptation resolves the contradiction between prompt processing and system performance.
3Reliability
If the receiver actively polls the shared memory location, then interrupts are not necessary, but the processor continuously utilizes CPU cycles instead of using them for other activities
Solution Approach 1:
The shared memory location acts as an intermediary that automatically generates interrupt signals when messages are written. This eliminates the need for the receiver to actively poll while still providing reliable message notification. The intermediary mechanism converts passive waiting into active notification only when necessary, resolving the contradiction between reliable notification and processor availability.
Data Source
AI summary
Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.