Deferred Page Clearing in Multiprocessor Systems
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Solution Overview
Problem
Current multiprocessor systems face significant overhead due to the hardware quiesce mechanism required for updating storage keys and invalidating page table entries, leading to increased system impact and latency in key updates and data clearing operations.
Innovation Solution
A method is introduced to logically clear data pages by setting a page initialize bit to a clear data value without physical clearing, with subsequent physical clearing occurring upon first access, and to minimize interprocessor communication by allowing stale storage keys to remain in local processor caches under certain conditions, reducing the need for quiesce operations and cache purges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware quiesce mechanism is used to update storage keys and invalidate page table entries, then system coherence and reliability are ensured, but system overhead and latency increase significantly
Solution Approach 1:
The patent applies preliminary action by setting the page initialize bit during page allocation or deallocation, before the actual page clearing operation. This allows the system to prepare the page state in advance, so that when the page is accessed, the clearing can be deferred or already completed, reducing the latency of storage key updates and page table invalidations.
Solution Approach 2:
The patent segments the page clearing operation from the page allocation/deallocation process by introducing a separate page initialize bit mechanism. This allows the coherence protocol to operate independently from the physical clearing operation, enabling parallel execution and reducing the critical path latency for storage key updates.
2Reliability
If physical clearing of data pages is performed immediately upon allocation or deallocation, then data integrity is ensured, but processing time and system resource utilization increase
Solution Approach 1:
The patent sets the page initialize bit as a preliminary action during page allocation or deallocation, marking the page as requiring initialization without immediately performing the costly physical clearing operation. This allows the system to maintain data integrity tracking while deferring the actual clearing work to a later time when the page is first accessed.
Solution Approach 2:
The patent introduces dynamic behavior by conditionally clearing pages based on access patterns. Pages with the page initialize bit set are cleared on first access rather than immediately, allowing the system to adapt the clearing timing to actual workload requirements and minimize unnecessary processing overhead for pages that may not be immediately used.
3Reliability
If all processors are quiesced during storage key updates, then cache coherence is maintained, but interprocessor communication overhead increases
Solution Approach 1:
The patent performs preliminary actions by setting the page initialize bit and updating page table entries before other processors need to access the affected pages. This allows the coherence protocol to establish the new state in advance, reducing the need for extensive interprocessor communication and quiesce operations when subsequent access occurs.
Solution Approach 2:
The patent introduces the page initialize bit as an intermediary mechanism that mediates between page allocation/deallocation and actual page clearing operations. This intermediary state allows processors to proceed without full quiesce protocols, as the page state is tracked through the initialize bit rather than requiring synchronous coordination across all processors.
4Measurement precision
If page table entries are invalidated with full cache purges, then translation accuracy is ensured, but access latency increases
Solution Approach 1:
The patent performs preliminary invalidation by setting the page initialize bit and updating page table entry validity bits before actual page access. This allows the translation accuracy to be ensured through proper bit setting, while the actual page clearing and cache purge operations are deferred, reducing access latency for subsequent translations.
Data Source
AI summary
Processing within a multiprocessor computer system is facilitated by: logically clearing a data page by setting, in association with invalidate page table entry or set storage key processing, a page initialize bit for the data page to a clear data value without physically clearing data from the data page; and subsequent to the setting of the page initialize bit, physically clearing data from the page in central storage responsive to a first access to the page with the page initialize bit set to the clear data value, thereby minimizing overall time required to both clear and subsequently access cleared page data. Setting of the page initialize bit may include setting a line clear bit for each page line to the clear data value, and allocating a state machine to clear each line responsive to the line being first accessed with the its line clear bit set.