Deferred Precision Receiver Processing for Lower-Power Symbol Detection
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Solution Overview
Problem
Digital communication systems face challenges in recovering signals embedded within noise and impairments while balancing power constraints and performance, necessitating efficient methods to reduce power usage in receiver signal processing without sacrificing performance.
Innovation Solution
Implementing deferred precision techniques in receiver signal processing, which involve partial equalization operations and utilizing information from hard decision regions to resolve symbols in deferred decision regions, thereby reducing computational power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full precision calculations are used in receiver signal processing, then signal recovery performance is improved, but power consumption increases
Solution Approach 1:
The patent segments the precision requirements by dividing signal processing into different regions: hard decision region where full precision is used, and deferred decision region where reduced precision is applied. This segmentation allows the system to use computational resources efficiently by applying full precision only where necessary while using reduced precision in regions where it suffices, thus reducing overall power consumption while maintaining signal recovery performance.
Solution Approach 2:
The patent applies partial precision (reduced precision) to signal processing operations in the deferred decision region, using only the necessary number of bits for that specific region rather than full precision throughout. This partial action approach reduces computational power consumption while still achieving adequate signal recovery performance in those regions, resolving the contradiction between performance and power usage.
2Use of energy by moving object
If reduced precision operations are used, then power consumption is reduced, but signal processing accuracy deteriorates
Solution Approach 1:
The patent implements local quality by applying different precision levels to different regions of the signal processing pipeline. The hard decision region receives full precision operations to maintain high accuracy where confidence is high, while the deferred decision region uses reduced precision operations to save power where the impact of precision reduction is acceptable. This localized differentiation of quality levels resolves the contradiction between power consumption and accuracy.
Solution Approach 2:
The patent uses feedback from the hard decision region to assist in resolving symbols in the deferred decision region. By using the information obtained from symbols falling within the hard decision region to assist in resolving symbols not landing within that region, the system compensates for the reduced precision in the deferred decision region, maintaining overall signal processing accuracy while reducing power consumption.
3Device complexity
If partial equalization is applied, then computational complexity is reduced, but equalization performance deteriorates
Solution Approach 1:
The patent segments the equalization process into two parts: a first equalization operation applied to all symbols, and a second equalization operation applied only to symbols in the deferred decision region. This segmentation reduces overall computational complexity by avoiding full equalization on all symbols while maintaining equalization performance where needed, resolving the contradiction between complexity and performance.
Solution Approach 2:
The patent applies partial equalization (reduced precision equalization) to symbols in the deferred decision region rather than applying full equalization to all symbols. This partial action reduces computational complexity while still providing sufficient equalization performance for those symbols, balancing the trade-off between complexity and performance.
Data Source
AI summary
A method may include receiving, at a receiver, a signal comprising a symbol. The method may include performing, at the receiver, a first operation using a number of most significant bits by gating a selected number of least significant bits. The method may include detecting, at the receiver, a symbol value of the symbol using the first operation.