Deferred-Push Register Control for Low-Latency Context Switching
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Solution Overview
Problem
Existing processor context switching methods incur significant latency and bus load due to the need to save and restore processor registers during interrupts, either through hardware or software mechanisms, which increase complexity and do not support nested interrupts effectively.
Innovation Solution
Implementing a processor with deferred-push registers and status registers that delay pushing registers to memory until they are actually changed, using processor-register control circuitry to manage these registers and minimize bus transactions and processor cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor registers are pushed to RAM during context switching, then register values are preserved for restoration, but processor latency and bus load increase significantly
Solution Approach 1:
The patent applies partial action by only pushing processor registers to the stack when they are actually modified during interrupt handling. Instead of pushing all registers unconditionally, the system tracks which registers are modified and pushes only those, reducing unnecessary bus transactions and latency while still preserving all necessary register values for restoration.
Solution Approach 2:
The interrupt handler automatically tracks and pushes only the registers it modifies, without requiring external control or pre-defined push lists. The system self-manages which registers need to be saved by monitoring its own register write operations, eliminating the need for unconditional pushing of all registers.
2Reliability
If all processor registers are pushed to stack during interrupt, then complete context is saved, but bus transactions and processor cycles are wasted on unchanged registers
Solution Approach 1:
The system performs partial pushing by identifying and pushing only the subset of registers that are actually modified during interrupt handling. The interrupt handler monitors its own register writes and pushes only those registers to the stack, avoiding wasted bus transactions on unchanged registers while ensuring complete preservation of the modified context.
Solution Approach 2:
The system uses feedback mechanisms where the interrupt handler monitors its own register modification actions and uses this information to determine which registers need to be pushed to the stack. This self-monitoring feedback loop ensures that only necessary registers are saved, optimizing bus transaction efficiency.
3Speed
If hardware automatically pushes registers before interrupt, then context switching is fast, but processor complexity and bus load increase
Solution Approach 1:
The interrupt handler itself performs the selective pushing of registers without requiring additional hardware circuitry. The handler monitors its own register writes and pushes only modified registers to the stack, achieving efficient context switching through software intelligence rather than hardware complexity.
Solution Approach 2:
The patent replaces hardware-based automatic register pushing with a software-based mechanism. Instead of using hardware circuitry to automatically push all registers, the system uses the interrupt handler's software logic to selectively push only modified registers, reducing hardware complexity while maintaining context switching speed.
4Adaptability or versatility
If software pushes registers in function prologue, then flexibility is improved, but latency increases due to instruction fetching and execution
Solution Approach 1:
The interrupt handler performs self-service by automatically tracking which registers it modifies and pushing only those to the stack. This eliminates the need for explicit prologue instructions to push all registers, reducing latency while maintaining the flexibility of selective register saving.
Solution Approach 2:
Instead of using software prologue to push all registers, the system uses partial action by pushing only the modified registers that the interrupt handler actually changes. This reduces the number of push instructions executed, lowering latency while preserving the flexibility of adaptive register saving.
Data Source
AI summary
A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.