Dynamic Huffman Table Generation Using Reduced-Bit Symbol Sorting
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Solution Overview
Problem
The existing DEFLATE compression algorithm requires a high number of latches and comparators for sorting symbol counts during dynamic Huffman table generation, which is expensive in terms of area, power, and timing/wiring considerations.
Innovation Solution
The solution involves mapping 24-bit symbol counts to 10-bit values using a 5-bit shift field and 5-bit mantissa, reducing the number of latches required for sorting and allowing for a dynamic Huffman tree generation with preserved relative frequency distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If 24-bit symbol counts are used for sorting during dynamic Huffman table generation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameter of symbol count representation from 24-bit fixed precision to a reduced-bit format (using shift field and mantissa). This parameter change reduces the latch count from 6,864 to 2,860 while maintaining sufficient precision for frequency-based sorting in the dynamic Huffman encoding context.
2Measurement precision
If 24-bit symbol counts are used for sorting, then measurement precision is improved, but area increases
Solution Approach 1:
The patent applies parameter changes by reducing the bit width of symbol counts from 24 bits to a compressed representation using shift and mantissa fields. This reduces the area required for storing and sorting symbol counts, freeing wafer area while maintaining the ability to perform accurate frequency-based sorting for Huffman tree generation.
3Measurement precision
If 24-bit symbol counts are used for sorting, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by changing the parameter of symbol count representation to a reduced-bit format. Fewer latches and comparators are required for sorting, which directly reduces dynamic power consumption in the static hardware component performing compression.
4Measurement precision
If 24-bit symbol counts are used for sorting, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent simplifies timing and wiring by reducing the bit width of symbol counts from 24 to a compressed format. This parameter change reduces the complexity of timing signals and wiring required for coordinating the sorting operation across multiple latches and comparators.
Data Source
AI summary
Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.