Deflected Stacked Semiconductor Chips for Substrate Miniaturization
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Solution Overview
Problem
The miniaturization of module substrates in semiconductor devices with stacked semiconductor chips is hindered by the complexity and cost of interconnection methods, particularly when using wire-bonding techniques, as the number of bonding leads increases, making it difficult to reduce the size of the module substrate effectively.
Innovation Solution
The solution involves deflecting the upper semiconductor chip to align with the border of the lower chip, allowing direct electrical connections between electrode pads and bonding leads, reducing the number of bonding leads on the module substrate and concentrating them into fewer lines, thereby simplifying the substrate and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding techniques are used to connect electrode pads to bonding leads, then electrical connections are established, but the number of bonding leads increases and module substrate miniaturization is hindered
Solution Approach 1:
The patent applies asymmetry by deflecting the upper semiconductor chip relative to the lower chip, creating an asymmetric stacked configuration. This deflection allows bonding leads to be concentrated on one side of the module substrate rather than requiring symmetric distribution, thereby reducing the overall substrate area while maintaining all necessary electrical connections.
Solution Approach 2:
The patent utilizes dimensional change by arranging bonding leads not only along the edges but also extending toward the center of the module substrate. This multi-dimensional lead arrangement optimizes space utilization and reduces the footprint of the module substrate while ensuring all electrode pads are properly connected.
2Reliability
If bonding leads are arranged in two rows along one side of the module substrate, then all electrode pads are connected, but the complexity and cost of interconnection increases
Solution Approach 1:
The patent merges the bonding lead arrangements by concentrating leads on one side of the module substrate and extending them toward the center, rather than maintaining separate two-row arrangements. This consolidation simplifies the interconnection structure, reduces the number of discrete lead groups, and lowers manufacturing complexity while preserving all necessary electrical connections.
3Length of moving object
If the upper semiconductor chip is brought close to the border portion of the lower chip, then wire length is reduced, but relay terminals are required on both sides of the lower chip
Solution Approach 1:
The patent extracts and eliminates the relay terminal structure from the lower semiconductor chip by implementing a deflected stacking configuration. This allows direct connection between the upper chip's electrode pads and the module substrate's bonding leads, removing the intermediate relay terminals and their associated complexity while maintaining short wire lengths.
Data Source
AI summary
A first semiconductor chip and a second semiconductor chip which form a stack are mounted on a module substrate by deflecting a center position of the semiconductor chips from the module substrate. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is shorter, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are directly connected with a wire. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is longer, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are combined with the corresponding bonding lead on the module substrate with a wire.