Deformed Metal Sphere Spacers for Stacked Semiconductor Devices
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Solution Overview
Problem
The challenge in semiconductor packaging is to shrink devices in both two and three dimensions while maintaining reliability and reducing costs, with the need for innovative methods that allow for device stacking and efficient assembly options to increase functional density and reduce device thickness, particularly for applications like hand-held wireless equipment.
Innovation Solution
A semiconductor device and method involving the use of deformed metal spheres as spacers to create a low-profile stacked structure with flip-chip and wire bond interconnections, allowing for flexible fabrication and alignment of semiconductor chips with reflow metal bonding and polymer underfill to ensure mechanical stability and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used, then device functionality can be maintained, but device size and volume cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, placing multiple semiconductor chips vertically on a single substrate. This dimensional change enables significant volume reduction while maintaining functionality, as chips are arranged in layers rather than requiring additional lateral space
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically on top of each other, with each chip containing functional circuits and interconnected through vertical interconnects. This nesting approach maximizes functional density within a compact volume
2Manufacturing precision
If chip stacking is implemented to reduce device thickness, then functional density increases, but alignment precision and manufacturing complexity increase
Solution Approach 1:
The patent incorporates alignment features and positioning structures during the chip fabrication process itself, such as predefined alignment marks and mechanical interlocking features on chip edges. These preliminary actions enable precise alignment during stacking without requiring complex post-fabrication alignment procedures
Solution Approach 2:
The patent introduces intermediate bonding layers and underfill materials between stacked chips that serve as mediators to accommodate minor misalignments and provide mechanical stability. These intermediary elements facilitate easier manufacturing by tolerating alignment variations while maintaining connection integrity
3Productivity
If feature sizes are shrunk to double functional complexity, then product functionality increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs advanced fabrication parameter control including precise temperature management during bonding, controlled reflow processes for interconnect formation, and optimized curing conditions for underfill materials. These parameter changes enable reliable manufacturing of fine-featured stacked devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, reliable, and cost-effective vertically integrated semiconductor systems with improved electrical performance and mechanical stability, suitable for various design and process variations, facilitating the miniaturization of semiconductor devices and accelerating time-to-market for innovative products.
Implementation Method 1
A reflow metal bonds the spacers to the second chip
Implementation Method 2
deformed sphere of non-reflow metal such as gold is placed on each contact pad... forming column-shaped spacers with a height
Data Source
AI summary
A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal (142) bonds the spacers to the second chip, while the spacers space the first and second chips by a gap (105a) wide enough for placing the wire spans to the second set pads.