Defrag Levels for Memory Buffer Data Loss

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Solution Overview

Problem

Memory devices experience data loss due to latency in writing data, particularly when the buffer receives data at a higher rate than it is transferred and written to the memory device, leading to frame drops in video data storage.

Innovation Solution

Implementing defrag levels to control the performance of memory devices, where different defrag levels perform defragmentation operations on varying portions of data before resuming user data writing, thereby optimizing write performance and reducing data loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If defragmentation operations are performed on larger portions of data, then data organization and reliability are improved, but write performance deteriorates due to longer periods where the memory device is busy and unable to write new user data

Engineering Contradiction:
Improvedata organizationVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides defragmentation operations into different levels (first defrag level and second defrag level) based on the amount of data processed. The first defrag level performs defrag operations on larger portions of data, while the second defrag level performs defrag operations on smaller portions of data, allowing the system to switch between levels to balance reliability and write performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically switches between different defrag levels based on buffer status. When the buffer is determined to be full during defrag operations at the first defrag level, the system transitions to the second defrag level to reduce defrag operation intensity and improve write performance, preventing data loss

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If the buffer receives data at a higher rate, then data capture completeness is improved, but data loss occurs because the buffer fills up faster than data can be written to the memory device

Engineering Contradiction:
Improvedata capture completenessVSAvoiddata loss
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements a feedback mechanism that continuously monitors buffer status during defrag operations. When the buffer is determined to be full, the system responds by switching from the first defrag level to the second defrag level, creating a closed-loop control system that adjusts defrag operation intensity based on real-time buffer conditions to prevent data loss

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts defrag operation intensity by switching between defrag levels based on buffer fullness, allowing the memory device to adapt to varying data reception rates and maintain reliable operation without data loss

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12235800B2Defrag levels to reduce data loss
Publication Date: 2025.02.25 MICRON TECHNOLOGY INC
  • US12235800B2 patent drawing
  • US12235800B2 patent drawing
  • US12235800B2 patent drawing

AI summary

Apparatuses, systems, and methods for using defrag levels to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include setting a first defrag level for a memory device, determining if a buffer is full while performing defrag operations on the memory device according to the first defrag level, setting a second defrag level for the memory device in response to determining the buffer is full while performing defrag operations according to the first defrag level.