Dehydrogenated Interlayer Dielectric Tensile Stress
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Solution Overview
Problem
Current methods for improving carrier mobility in MOS transistors, such as applying stress to channel regions, do not effectively enhance the operational characteristics of semiconductor devices, particularly in achieving high electron mobility and reliability.
Innovation Solution
The method involves forming a first interlayer dielectric layer with a tensile stress of 200 MPa or more on NMOS transistors by dehydrogenating layers like O3-TEOS using plasma, UV, or thermal treatments in a dehydrogenation gas atmosphere, and subsequent formation of additional interlayer dielectric layers with controlled stress, along with a capping layer to prevent moisture and ion penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stress application methods (ion implantation or liner layers) are used to improve carrier mobility, then electron or hole mobility can be enhanced, but the overall operational characteristics and reliability of semiconductor devices are not sufficiently improved
Solution Approach 1:
The patent changes the stress parameter from conventional methods to dehydrogenated interlayer dielectric stress. By dehydrogenating the interlayer dielectric layer through plasma treatment, UV treatment, or thermal treatment in a dehydrogenation gas atmosphere, the layer generates tensile stress of 200 MPa or more, which effectively enhances electron mobility in NMOS transistors while improving overall device reliability
Solution Approach 2:
The patent replaces conventional mechanical stress application methods (ion implantation or liner layer formation) with a chemical treatment approach. By applying dehydrogenation treatment to the interlayer dielectric layer, the desired mechanical stress is generated through chemical modification rather than direct mechanical application, achieving both mobility enhancement and improved reliability
2Productivity
If dehydrogenation treatment is applied to the first interlayer dielectric layer to increase tensile stress, then electron mobility and current driving ability are improved, but additional process steps are required
Solution Approach 1:
The patent applies dehydrogenation treatment to the first interlayer dielectric layer before forming subsequent interlayer dielectric layers. This preliminary action ensures that the tensile stress is established early in the manufacturing process, allowing the stress to be maintained through subsequent processing steps while improving electron mobility
Solution Approach 2:
The dehydrogenation treatment serves multiple functions: it generates the required tensile stress in the first interlayer dielectric layer, improves electron mobility in NMOS transistors, and enhances device reliability. This multi-functional approach reduces the need for separate process steps dedicated solely to stress generation
3Reliability
If a capping layer is formed to prevent moisture and ion penetration, then gate dielectric layer reliability is improved, but device structure becomes more complex
Solution Approach 1:
The patent forms a capping layer over the dehydrogenated first interlayer dielectric layer to prevent moisture and external ions from penetrating into the layer. This beforehand cushioning protects the stress-generating layer from environmental degradation, maintaining device reliability over time
Solution Approach 2:
The capping layer is implemented as a thin film structure that provides protection against moisture and ion penetration. This thin film approach minimizes the added structural complexity while effectively maintaining gate dielectric layer reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases electron mobility and current driving ability of NMOS transistors by up to 10% and improves the reliability of the gate dielectric layer by reducing hot electron injection effects, while maintaining PMOS transistor performance.
Implementation Method 1
dehydrogenating the first interlayer dielectric layer may include performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere
Implementation Method 2
Dehydrogenating the first interlayer dielectric layer may include performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere
Implementation Method 3
Dehydrogenating the first interlayer dielectric layer may include performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere
Implementation Method 4
Dehydrogenating the first interlayer dielectric layer may include performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere
Implementation Method 5
The capping layer may obstruct or hinder moisture and/or external ions from penetrating into the first interlayer dielectric layer
Data Source
AI summary
Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.