Multi-field Deinterlacer Memory and Bandwidth Reduction
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Solution Overview
Problem
Conventional multi-field deinterlacers face challenges in minimizing on-chip memory size and peak DRAM bandwidth requirements, particularly when handling interlaced video signals, as they often require significant buffering and increased bandwidth to maintain continuous output.
Innovation Solution
A method and system that buffer upper and lower line pixels to generate a deinterlaced output frame, utilizing a pixel processor with FIFOs and a line reorder to selectively alternate between buffered pixels, reducing the need for excessive memory and bandwidth by optimizing pixel processing and reordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-field deinterlacers buffer all input lines to maintain continuous output, then output continuity is improved, but on-chip memory size increases
Solution Approach 1:
The patent divides the buffering requirement into two separate FIFO structures: one for upper field lines and one for lower field lines. This segmentation allows the system to buffer only the necessary lines from each field separately, reducing the total memory size compared to buffering all lines in a single large buffer, while still maintaining continuous output capability.
Solution Approach 2:
The patent performs preliminary buffering of upper and lower field lines in separate FIFOs before the deinterlacing process. By preparing the lines in advance in organized groups and using line reorder logic to select and combine them, the system maintains continuous output without requiring large on-chip memory for all lines simultaneously.
2Productivity
If conventional multi-field deinterlacers use multiple field stores read in parallel, then processing speed is improved, but peak DRAM bandwidth requirements increase
Solution Approach 1:
The patent segments the parallel read operations into two separate single-field deinterlacing operations, one for the upper field and one for the lower field. Each operation reads from its own dedicated FIFO, eliminating the need for simultaneous parallel reads from multiple field stores. This maintains processing throughput while reducing peak DRAM bandwidth requirements.
Solution Approach 2:
The patent uses periodic alternation between processing upper field lines and lower field lines through the line reorder logic. Instead of simultaneous parallel processing that creates peak bandwidth demands, the system periodically switches between fields, smoothing the DRAM access pattern and reducing peak bandwidth requirements while maintaining overall processing speed.
3Reliability
If FIFO is added at each parallel input to handle intermittent activation, then output continuity is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal buffering structure where two FIFOs (for upper and lower fields) share the same control logic and line reorder mechanism. This multi-functional approach allows the same buffering infrastructure to handle both fields, reducing overall complexity compared to having separate FIFOs and control logic for each parallel input, while still ensuring continuous output.
Data Source
AI summary
In a video system, a method and system for minimizing both on-chip memory size and peak DRAM bandwidth requirements for multi-field deinterlacers are provided. Present line pixels and absent line pixels may be determined and may be ordered into upper line pixels and lower line pixels based on whether an interlaced output frame is top field or bottom field originated. Upper line pixels may be buffered in an upper line FIFO that may hold half a video line and lower line pixels may be buffered in an lower line FIFO that may hold a video line. A source switch and a line length counter may be used to assemble the deinterlaced output frame by selecting from the buffered upper line pixels and the buffered lower line pixels. The deinterlaced output frame may be buffered in an output FIFO.