Convolution Time De-Interleaver Buffering for Memory Bandwidth Efficiency
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Solution Overview
Problem
Convolution time de-interleavers require large circuit area and higher hardware costs, and replacing shift registers with memory leads to inefficient memory bandwidth utilization due to discontinuous write addresses and increased output time.
Innovation Solution
A convolution time de-interleaver design utilizing an output buffer, input buffer, memory, input control unit, output control unit, and controller, where data is written to memory in batches to optimize bandwidth usage, with each memory block having a priority write order and output register units providing different delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shift registers are replaced with memory in convolution time de-interleaver, then hardware cost and circuit area are reduced, but memory bandwidth utilization becomes inefficient due to discontinuous write addresses
Solution Approach 1:
The memory is divided into multiple memory blocks, each handling specific data streams. This segmentation allows continuous addressing within each block while maintaining the overall de-interleaving function, thus improving memory bandwidth utilization without sacrificing hardware cost benefits.
Solution Approach 2:
Data is pre-organized and written to memory blocks in a predetermined sequence before actual processing. This preliminary arrangement ensures that subsequent read operations can proceed continuously, eliminating address discontinuity issues and maximizing memory bandwidth efficiency.
2Ease of manufacture
If shift registers are replaced with memory in convolution time de-interleaver, then hardware cost is reduced, but output time increases
Solution Approach 1:
The memory system is designed to maintain continuous data flow from input to output through coordinated read/write operations. By ensuring that data is always available for the next processing stage, the system avoids idle time and maintains high throughput despite using memory instead of faster shift registers.
Solution Approach 2:
Control units act as intermediaries between memory and processing stages, managing data transfer timing and sequence. These control units optimize the interaction between memory's natural access patterns and the processing requirements, minimizing delays and maintaining efficient output rates.
3Reliability
If multiple shift register groups with different delay lengths are used, then data interleaving effectiveness is improved, but circuit area and hardware cost increase
Solution Approach 1:
Multiple delay functions that would traditionally require separate shift register groups are merged into a single memory structure. By using memory's inherent storage capabilities and control logic, the system achieves the same delay diversity with significantly reduced circuit area, maintaining data interleaving effectiveness while lowering hardware costs.
Solution Approach 2:
Instead of using fixed-structure shift registers with different physical lengths, the system uses memory with programmable or dynamically configurable delay parameters. This allows the same hardware resource to provide multiple delay lengths by changing operational parameters, reducing overall circuit area while maintaining interleaving effectiveness.
Data Source
AI summary
A convolution time de-interleaver includes an input buffer, an output buffer, a memory, an input control circuit, an output control circuit, and a controller. The memory includes a plurality of memory blocks. The input control circuit sequentially outputs a plurality of entries of data to a plurality of input register unit groups of the input buffer respectively and correspondingly. After a predetermined amount of data have been written to the input buffer, the controller writes part of data stored in the input buffer to a corresponding memory block. After the plurality of memory blocks are written, the controller writes data stored in a corresponding memory block to the output buffer. The output control circuit sequentially outputs a plurality of pieces of data stored in a plurality of output register unit groups of the output buffer.