Deinterleaver Memory Layout for Lower-Power Burst Error Correction

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Solution Overview

Problem

Conventional convolutional interleavers and deinterleavers in satellite DMB systems face complexity and high power consumption due to increased memory access frequency and complex address generation, especially when dealing with burst errors, which complicates the interface with outer memory and increases power consumption.

Innovation Solution

A deinterleaving apparatus and method that utilizes an inner memory to store address information and values corresponding to the outer memory, reducing the need for multiple counters and registers, and employing a simplified address generation scheme to decrease access frequency to the outer memory, thereby reducing power consumption and simplifying the interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional convolutional interleavers and deinterleavers are used to handle burst errors, then error correction capability is improved, but device complexity and power consumption increase due to frequent memory access and complex address generation

Engineering Contradiction:

Improveerror correction capabilityVSAvoidinterface complexity with outer memory

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the memory system into two segments: an inner memory (503) for storing address information and values corresponding to outer memory, and an outer memory for storing actual data. This segmentation allows the inner memory to handle address generation locally, reducing the complexity of the interface with the outer memory while maintaining error correction capability through the interleaving structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The inner memory acts as an intermediary between the deinterleaver and the outer memory. It stores and manages address information, generating addresses for outer memory access without requiring complex address generation logic at the outer memory interface. This intermediary structure simplifies the interface complexity while preserving the ability to correct burst errors through proper address management.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If conventional convolutional interleavers and deinterleavers are used to handle burst errors, then error correction capability is improved, but power consumption increases due to frequent memory access

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

By segmenting the memory system into inner and outer memories, the patent reduces the access frequency to the power-consuming outer memory. The inner memory handles address generation and storage locally, minimizing the number of times data needs to be transferred to and from the outer memory, thereby reducing overall power consumption while maintaining error correction functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The inner memory serves as an intermediary that caches address information, reducing the need for frequent accesses to the outer memory. By generating and storing addresses locally in the inner memory, the system minimizes the energy-consuming memory access operations to the outer memory while still enabling effective error correction through the interleaving structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If multiple counters and registers are used for address generation in conventional systems, then address accuracy is improved, but device complexity increases

Engineering Contradiction:

Improveaddress generation accuracyVSAvoidnumber of counters and registers

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple counters and registers into a single inner memory structure. Instead of using separate counters and registers for address generation, the inner memory stores all necessary address information in a consolidated manner, achieving the same address generation accuracy with significantly reduced device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The inner memory creates a simplified copy of the address generation logic by storing pre-computed address information. Rather than implementing complex counter and register circuits, the system uses the inner memory to hold address values that would otherwise be generated by multiple counters and registers, maintaining address accuracy while reducing hardware complexity.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS7526712B2Deinterleaving apparatus and method using inner memory and outer memory

Publication Date: 2009.04.28 SAMSUNG ELECTRONICS CO LTD

AI summary

An apparatus and a method for deinterleaving using an inner memory and an outer memory. The apparatus includes data receiving apparatus of a mobile equipment in a mobile communication system including the mobile equipment and a base station for transmitting data to the mobile equipment through a radio channel. The apparatus includes a deinterleaving unit having a deinterleaver and an outer memory separately located with the deinterleaver. The deinterleaver stores address information including an address of the outer memory and values corresponding to the address of the outer memory in an inner memory. The outer memory stores the data to be deinterleaved, and a decoder for decoding the deinterleaved data.